Low capacitance over-voltage protection thyristor device

Abstract

An over-voltage protection thyristor has reduced junction capacitance making it suitable for use in high bandwidth applications. The reduced capacitance is achieved through the introduction of a deep base region. The deep base region has a graded doping concentration which reduces with depth into the substrate. The thyristor is useful for protecting sensitive electrical equipment from transient surges.

1 . An over-voltage protection thyristor device, comprising: 
 a substrate semiconductor material of a first conductivity type, the substrate having a first outer surface and a second outer surface;    a shallow base region of a second conductivity type extending from the first outer surface into the substrate;    an emitter of the first conductivity type extending from the first outer surface into the shallow base region, the emitter having a depth that is less than the shallow base region;    a deep base region of the second conductivity type extending into the substrate from the second outer surface, the deep base region having a graded concentration reducing into the substrate such that the capacitance between the deep base region and the substrate is reduced.    
     
     
         2 . An over-voltage protection thyristor device according to  claim 1 , comprising a buried region of the first conductivity type extending beyond the shallow base region into the substrate, the buried region having a higher doping concentration than the substrate.  
     
     
         3 . An over-voltage protection thyristor device according to  claim 2 , wherein the doping concentration in the buried region is selected in accordance with a desired breakdown voltage for the over-voltage protection thyristor device.  
     
     
         4 . An over-voltage protection thyristor device according to  claim 2 , wherein the buried region has the same lateral extent as the shallow base region.  
     
     
         5 . An over-voltage protection thyristor device according to  claim 2 , wherein the buried region and the deep base region are plug shaped regions and the device comprises a pair of laterally separated anti-parallel thyristors formed on a common substrate.  
     
     
         6 . An over-voltage protection thyristor device according to  claim 3 , wherein the buried region is at least 86 microns deep.  
     
     
         7 . An over-voltage protection thyristor device according to  claim 3 , wherein the shallow base region for each one of the pair of devices extends into the deep base region for the other of the pair of devices, the deep base region extending into the substrate beyond the shallow base regions.  
     
     
         8 . An over-voltage protection thyristor device according to  claim 1 , wherein the substrate has a low doping concentration.  
     
     
         9 . An over-voltage protection thyristor device according to  claim 1 , wherein the first conductivity type semiconductor material comprises n-type impurities and the second conductivity type semiconductor material comprises p-type impurities.  
     
     
         10 . An over-voltage protection thyristor device according to  claim 1 , wherein the first conductivity type semiconductor material comprises p-type impurities and the second conductivity type semiconductor material comprises n-type impurities.  
     
     
         11 . An over-voltage protection thyristor device according to  claim 1 , wherein the emitter region has a plurality of perforations therethrough, the shallow base region extending through the perforations to the first outer surface.  
     
     
         12 . An over-voltage protection thyristor device according to  claim 11 , wherein the size and number of perforations in accordance with a desired holding current for the device.  
     
     
         13 . An over-voltage protection thyristor device according to  claim 1 , wherein the shallow base region is between 29 and 33 microns deep.  
     
     
         14 . An over-voltage protection thyristor device according to  claim 1 , wherein the deep base region is between 109 and 130 microns deep.  
     
     
         15 . An over-voltage protection thyristor device according to  claim 1 , wherein the emitter is between 9 and 12 microns deep.  
     
     
         16 . An over-voltage protection thyristor device according to  claim 1 , comprising a conductive electrode layer on each of the first and second outer surfaces.  
     
     
         17 . An over-voltage protection thyristor device according to  claim 16 , wherein the conductive electrode layer comprises aluminum.  
     
     
         18 . An over-voltage protection thyristor device according to  claim 17 , comprising one or more protective outer layers selected from the group consisting of titanium, nickel and silver.  
     
     
         19 . An over-voltage protection thyristor device according to  claim 1 , used for protecting electrical equipment from line transients.  
     
     
         20 . A method of fabricating an over-voltage protection thyristor device on a substrate semiconductor material of a first conductivity type, the substrate having a having a first outer surface and a second outer surface, the method comprising the steps of: 
 forming a shallow base region of a second conductivity type extending from the first outer surface into the substrate;    forming an emitter of the first conductivity type extending from the first outer surface into the shallow base region, the emitter having a depth that is less than the shallow base region;    forming a deep base region of the second conductivity type extending into the substrate from the second outer surface, the deep base region having a graded concentration reducing into the substrate such that the capacitance between the deep base region and the substrate is reduced.    
     
     
         21 . A method according to  claim 20 , comprising forming a buried region of the first conductivity type extending beyond the shallow base region into the substrate, the buried region having a higher doping concentration than the substrate.  
     
     
         22 . A method according to  claim 21 , wherein forming the buried region comprises doping the substrate with phosphorous.  
     
     
         23 . A method according to  claim 20 , wherein forming the shallow base region comprises doping the substrate with boron nitride.  
     
     
         24 . A method according to  claim 20 , wherein forming the emitter comprises overdoping the shallow base region with impurities of the first conductivity type.  
     
     
         25 . A method according to  claim 24 , wherein the impurities of the first conductivity type comprise phosphorous.  
     
     
         26 . A method according to  claim 20 , wherein forming the deep base region comprises doping the substrate with boron.