Complementary metal-oxide semiconductor (CMOS) devices including a thin-body channel and dual gate dielectric layers and methods of manufacturing the same

Abstract

A complementary metal-oxide semiconductor (CMOS) device includes an NMOS thin body channel including a silicon epitaxial layer. An NMOS insulating layer is formed on a surface of the NMOS thin body channel and surrounds the NMOS thin body channel. An NMOS metal gate is formed on the NMOS insulating layer. The CMOS device further includes a p-channel metal-oxide semiconductor (PMOS) transistor including a PMOS thin body channel including a silicon epitaxial layer. A PMOS insulating layer is formed on a surface of and surrounds the PMOS thin body channel. A PMOS metal gate is formed on the PMOS insulating layer. The NMOS insulating layer includes a silicon oxide layer and the PMOS insulating layer includes an electron-trapping layer, the NMOS insulating layer includes a hole trapping dielectric layer and the PMOS insulating layer includes a silicon oxide layer, or the NMOS insulating layer includes a hole-trapping dielectric layer and the PMOS insulating layer includes an electron-trapping dielectric layer.

1 . A complementary metal-oxide semiconductor (CMOS) device, comprising: 
 an n-channel metal-oxide semiconductor (NMOS) transistor comprising: 
 an NMOS thin body channel comprising a silicon epitaxial layer;  
 an NMOS insulating layer formed on a surface of the NMOS thin body channel and surrounding the NMOS thin body channel; and  
 an NMOS metal gate formed on the NMOS insulating layer; and  
   a p-channel metal-oxide semiconductor (PMOS) transistor comprising: 
 a PMOS thin body channel comprising a silicon epitaxial layer;  
 a PMOS insulating layer formed on a surface of and surrounding the PMOS thin body channel; and  
 a PMOS metal gate formed on the PMOS insulating layer;  
   wherein the NMOS insulating layer comprises a silicon oxide layer and the PMOS insulating layer comprises an electron-trapping layer, the NMOS insulating layer comprises a hole trapping dielectric layer and the PMOS insulating layer comprises a silicon oxide layer, or the NMOS insulating layer comprises a hole-trapping dielectric layer and the PMOS insulating layer comprises an electron-trapping dielectric layer.    
   
   
       2 . The CMOS device of  claim 1 , wherein the electron-trapping dielectric layer comprises an Al 2 O 3  layer.  
   
   
       3 . The CMOS device of  claim 2 , wherein the PMOS insulating layer further comprises a PMOS interface layer interposed between the PMOS thin body channel and the Al 2 O 3  layer.  
   
   
       4 . The CMOS device of  claim 3 , wherein the PMOS interface layer comprises a silicon oxide layer, a silicon oxynitride layer, and/or a silicate layer.  
   
   
       5 . The CMOS device of  claim 1 , wherein the hole-trapping dielectric layer comprises an HfO 2  layer.  
   
   
       6 . The CMOS device of  claim 5 , wherein the NMOS insulating layer further comprises an NMOS interface layer interposed between the surface of the NMOS thin body channel and the HfO 2  layer.  
   
   
       7 . The CMOS device of  claim 6 , wherein the NMOS interface layer comprises a silicon oxide layer, a silicon oxynitride layer, and/or a silicate layer.  
   
   
       8 . The CMOS device of  claim 1 , wherein each of the NMOS thin body channel and the PMOS thin body channel comprises an undoped silicon epitaxial layer.  
   
   
       9 . The CMOS device of  claim 1 , wherein each of the NMOS thin body channel and the PMOS thin body channel comprises an N-doped silicon epitaxial layer.  
   
   
       10 . The CMOS device of  claim 1 , wherein the NMOS metal gate and the PMOS metal gate comprise identical materials.  
   
   
       11 . The CMOS device of  claim 10 , wherein the NMOS metal gate and the PMOS metal gate comprise TiN.  
   
   
       12 . The CMOS device of  claim 1 , wherein the hole-trapping dielectric layer comprises an HfO 2  layer and the electron-trapping dielectric layer comprises an Al 2 O 3  layer.  
   
   
       13 . A complementary metal-oxide semiconductor (CMOS) device, comprising: 
 an n-channel metal-oxide semiconductor (NMOS) transistor comprising: 
 an NMOS active channel pattern including a plurality of NMOS thin body channels stacked vertically and at least one tunnel interposed between the NMOS thin body channels formed on a first region of a semiconductor substrate;  
 an NMOS insulating layer surrounding a surface of the NMOS thin body channel; and  
 an NMOS metal gate filling the tunnel and surrounding the NMOS insulating layer; and  
   a p-channel metal-oxide semiconductor (PMOS) transistor comprising: 
 a PMOS active channel pattern including a plurality of PMOS thin body channels stacked vertically and at least one tunnel interposed between the PMOS thin body channels formed on a second region of the semiconductor substrate;  
 a PMOS insulating layer surrounding a surface of the PMOS thin body channel; and  
 a PMOS metal gate filling the tunnel and surrounding the PMOS insulating layer;  
   wherein the NMOS insulating layer comprises a silicon oxide layer and the PMOS insulating layer comprises an electron-trapping layer, the NMOS insulating layer comprises a hole trapping dielectric layer and the PMOS insulating layer comprises a silicon oxide layer, or the NMOS insulating layer comprises a hole-trapping dielectric layer and the PMOS insulating layer comprises an electron-trapping dielectric layer.    
   
   
       14 . The CMOS device of  claim 13 , further comprising: 
 an NMOS source/drain region formed on both sides of the NMOS active channel pattern and connected to the NMOS thin body channels; and    a PMOS source/drain region formed on both sides of the PMOS active channel pattern and connected to the NMOS thin body channels.    
   
   
       15 . The CMOS device of  claim 13 , further comprising: 
 an NMOS source/drain extension layer interposed between the NMOS thin body channel and the NMOS source/drain region; and    a PMOS source/drain extension layer interposed between the PMOS thin body channel and the PMOS source/drain region.    
   
   
       16 . The CMOS device of  claim 13 , wherein each of the NMOS thin body channels and the PMOS thin body channels comprises an undoped silicon epitaxial layer.  
   
   
       17 . The CMOS device of  claim 13 , wherein each of the NMOS thin body channels and the PMOS thin body channels comprises an N-doped silicon epitaxial layer.  
   
   
       18 . The CMOS device of  claim 13 , wherein the NMOS metal gate and the PMOS metal gate comprise identical materials.  
   
   
       19 . The CMOS device of  claim 18 , wherein the NMOS metal gate and the PMOS metal gate comprise TiN.  
   
   
       20 . The CMOS device of  claim 13 , wherein the hole-trapping dielectric layer comprises an HfO 2  layer.  
   
   
       21 . The CMOS device of  claim 13 , wherein the electron-trapping dielectric layer comprises an Al 2 O 3  layer.  
   
   
       22 . A method of manufacturing a complementary metal-oxide semiconductor (CMOS) device, comprising: 
 forming a preliminary layer for forming a channel on a semiconductor substrate in which an NMOS region and a PMOS region are defined, the preliminary layer including a sacrificial layer and a thin body channel layer;    patterning the preliminary layer for forming the channel to form a preliminary pattern for forming an NMOS channel in the NMOS region and a preliminary pattern for forming a PMOS channel in the PMOS region;    anisotropically etching the ends of the preliminary patterns for forming the NMOS and PMOS channels until a surface of the semiconductor substrate is exposed to form a groove, thereby forming a pattern for forming the NMOS channel in the NMOS region and a pattern for forming the PMOS channel in the PMOS region;    forming an NMOS source/drain region and a PMOS source/drain region by filling the groove with a material layer;    forming an NMOS thin body channel and a PMOS thin body channel by removing a residual sacrificial layer of the patterns for forming the NMOS and PMOS thin body channels;    forming an NMOS insulating layer surrounding the NMOS thin body channel on a surface of the NMOS thin body channel when the PMOS region is masked;    forming an NMOS metal gate pattern on a surface of and surrounding the NMOS insulating layer;    forming a PMOS insulating layer surrounding the PMOS thin body channel on a surface of the PMOS thin body channel when the NMOS region is masked; and    forming a PMOS metal gate pattern on a surface of and surrounding the PMOS insulating layer;    wherein the NMOS insulating layer comprises a silicon oxide layer and the PMOS insulating layer comprises an electron-trapping layer, the NMOS insulating layer comprises a hole trapping dielectric layer and the PMOS insulating layer comprises a silicon oxide layer, or the NMOS insulating layer comprises a hole-trapping dielectric layer and the PMOS insulating layer comprises an electron-trapping dielectric layer.    
   
   
       23 . The method of  claim 22 , wherein the forming the NMOS insulating layer and the forming the NMOS metal gate pattern are preceded by the forming a PMOS insulating layer and the forming a PMOS metal gate pattern.  
   
   
       24 . The method of  claim 22 , further comprising, before the forming the NMOS and PMOS source/drain regions, trimming the patterns for forming the NMOS and PMOS channels.  
   
   
       25 . The method of  claim 22 , further comprising, before the forming the NMOS and PMOS source/drain regions, forming an NMOS source/drain extension layer and a PMOS source/drain extension layer on sidewalls of the patterns for forming the NMOS and PMOS channels, respectively.  
   
   
       26 . The method of  claim 25 , wherein the NMOS and PMOS source/drain extension layers are formed by selective epitaxial growth (SET).  
   
   
       27 . The method of  claim 22 , wherein the sacrificial layer comprises silicon germanium (SiGe) and the NMOS and PMOS thin body channels comprise silicon.  
   
   
       28 . The method of  claim 27 , wherein the preliminary layer for forming the channel comprises a first sacrificial layer, a first silicon layer, a second sacrificial layer, and a second silicon layer stacked sequentially.  
   
   
       29 . The method of  claim 27 , wherein the preliminary layer for forming the channel comprises undoped silicon.  
   
   
       30 . The method of  claim 27 , wherein the preliminary layer for forming the channel comprises N-doped silicon.  
   
   
       31 . The method of  claim 22 , wherein the NMOS insulating layer comprises an HfO 2  layer  
   
   
       32 . The method of  claim 31 , further comprising, before the forming the NMOS insulating layer, forming an NMOS interface layer on a surface of the NMOS thin body channel.  
   
   
       33 . The method of  claim 32 , wherein the NMOS interface layer comprises a silicon oxide layer, a silicon oxynitride layer, and/or a silicate layer.  
   
   
       34 . The method of  claim 22 , wherein the PMOS insulating layer comprises an Al 2 O 3  layer.  
   
   
       35 . The method of  claim 34 , further comprising, before the forming the PMOS insulating layer, forming a PMOS interface layer on a surface of the PMOS thin body channel.  
   
   
       36 . The method of  claim 35 , wherein the PMOS interface layer comprises a silicon oxide layer, a silicon oxynitride layer, and/or a silicate layer.  
   
   
       37 . The method of  claim 22 , wherein the NMOS metal gate and the PMOS metal gate comprise identical materials.  
   
   
       38 . The method of  claim 37 , wherein the NMOS metal gate and the PMOS metal gate comprise TiN.  
   
   
       39 . The method of  claim 22 , wherein the NMOS metal gate and the PMOS metal gate comprise different materials.  
   
   
       40 . A method of manufacturing a complementary metal-oxide semiconductor (CMOS) device, comprising: 
 forming a preliminary layer for forming a channel on a semiconductor substrate in which an NMOS region and a PMOS region are defined, the preliminary layer including a sacrificial layer and a thin body channel layer;    forming a first mask pattern defining an active region on the preliminary layer for forming a channel;    etching the preliminary layer for forming the channel using the first mask pattern as an etch mask to form a preliminary pattern for forming an NMOS channel in the NMOS region and a preliminary pattern for forming a PMOS channel in the PMOS region;    forming a second mask pattern on the preliminary patterns for forming NMOS and PMOS channels to expose both ends of the preliminary patterns for forming NMOS and PMOS channels and to define a channel region;    anisotropically etching the preliminary patterns for forming the NMOS and PMOS channels until a surface of the semiconductor substrate is exposed using the second mask pattern as an etch mask to form a groove, thereby forming a pattern for forming the NMOS channel in the NMOS region and a pattern for forming the PMOS channel in the PMOS region;    forming an NMOS source/drain region and a PMOS source/drain region by filling the groove with a material layer;    forming a third mask pattern covering the NMOS and PMOS source/drain regions and exposing an upper surface of the pattern for forming the NMOS and PMOS channels;    forming a fourth mask pattern covering the PMOS region;    exposing a side of the pattern for forming the NMOS channel using the third mask pattern of the NMOS region as an etch mask;    selectively removing a residual sacrificial layer of the pattern for forming the NMOS channel to form an NMOS thin body channel;    forming an NMOS insulating layer on a surface of and surrounding the NMOS thin body channel;    forming an NMOS metal gate pattern on and surrounding the NMOS insulating layer;    removing the fourth mask pattern;    forming a fifth mask pattern covering the NMOS region;    exposing a side of the pattern for forming the PMOS channel using the third mask pattern of the PMOS region as an etch mask;    selectively removing a residual sacrificial layer of the pattern for forming the PMOS channel to form a PMOS thin body channel;    forming a PMOS insulating layer on a surface of and surrounding the PMOS thin body channel;    forming a PMOS metal gate pattern on and surrounding the PMOS insulating layer; and    removing the fifth mask pattern;    wherein the NMOS insulating layer comprises a silicon oxide layer and the PMOS insulating layer comprises an electron-trapping layer, the NMOS insulating layer comprises a hole trapping dielectric layer and the PMOS insulating layer comprises a silicon oxide layer, or the NMOS insulating layer comprises a hole-trapping dielectric layer and the PMOS insulating layer comprises an electron-trapping dielectric layer.    
   
   
       41 . The method of  claim 40 , wherein, after the forming the preliminary patterns for forming the NMOS and PMOS channels, forming a shallow trench isolation layer in a portion of the semiconductor substrate on which the preliminary patterns for forming the NMOS and PMOS channels are not formed; and 
 wherein the exposing a side of the patterns for forming the NMOS and PMOS channels comprises etching the shallow trench isolation layer.    
   
   
       42 . The method of  claim 40 , further comprising trimming the patterns for forming the NMOS and PMOS channels between the forming patterns for forming the NMOS and PMOS channels and the forming the NMOS and PMOS source/drain region.  
   
   
       43 . The method of  claim 40 , further comprising forming an NMOS source/drain extension layer and a PMOS source/drain extension layer on sidewalls of the patterns for forming the NMOS and PMOS channels, respectively.  
   
   
       44 . The method of  claim 40 , wherein the sacrificial layer comprises silicon germanium (SiGe) and the NMOS and PMOS thin body channels comprises silicon.  
   
   
       45 . The method of  claim 44 , wherein the preliminary layer for forming the channel comprises undoped silicon.  
   
   
       46 . The method of  claim 44 , wherein the preliminary layer for forming the channel comprises N-doped silicon.  
   
   
       47 . The method of  claim 44 , wherein the second mask pattern comprises silicon oxide.  
   
   
       48 . The method of  claim 44 , wherein the third mask pattern comprises silicon nitride.  
   
   
       49 . The method of  claim 40 , wherein the NMOS insulating layer comprises an HfO 2  layer.  
   
   
       50 . The method of  claim 40 , wherein the PMOS insulating layer comprise an Al 2 O 3  layer.