Phase-change memory device using chalcogenide compound as the material of memory cells

Abstract

A phase-change memory device includes memory cells, a memory cell array, a first electrode layer, a word line, and a bit line. The memory cell includes a phase-change layer formed on a semiconductor substrate. The memory cell array has the memory cells arranged in a matrix. The phase change layer includes first regions which contact the semiconductor substrate in units of memory cells and a second region which connects the first regions arranged in a same column. The first electrode layer is formed on the second region. A contact area of each first region and the semiconductor substrate is smaller than a contact area of the second region and the first electrode layer. The bit line is electrically connected to the first electrode layer. The bit line is connects in common the phase-change layers of the memory cells arranged in the same column.

1 - 9 . (canceled)  
     
     
         10 . A phase-change memory device comprising: 
 memory cells including a phase-change layer formed on a semiconductor substrate, the phase-change layer showing an amorphous-crystalline phase change;    a memory cell array which has the memory cells arranged in a matrix;    a word line which connects the memory cells arranged in a same row; and    a bit line which connects the phase-change layers of the memory cells arranged in a same column, each of the phase-change layers including first regions which contact the semiconductor substrate in units of memory cells and a second region which connects the first regions arranged in the same column and which contacts the bit line, a contact area of each first region and the semiconductor substrate being smaller than a contact area of the second region and the bit line.    
     
     
         11 . The device according to  claim 10 , wherein the bit line includes a first metal layer and a second metal layer contacting the second region.  
     
     
         12 . The device according to  claim 11 , wherein the first metal layer has a lower resistance than the second metal layer.  
     
     
         13 . The device according to  claim 10 , wherein each phase-change layer further includes a third region interposed between the second region and each first region, the third region having a width greater than the contact area of the each first region and the semiconductor substrate, and less than the contact area of the second region and the bit line.  
     
     
         14 . The device according to  claim 10 , further comprising a resistor element formed on the semiconductor substrate with respect to each memory cell and provided between the semiconductor substrate and the first region of each phase-change layer, a contact area of the resistor element and each first region being smaller than the contact area of the second region and the bit line.  
     
     
         15 . The device according to  claim 10 , further comprising a second electrode layer interposed between each first region and the semiconductor substrate.  
     
     
         16 . The device according to  claim 15 , wherein an upper surface of the second electrode layer opposing each first region is larger than a surface of each first region opposing the second electrode layer.  
     
     
         17 . The device according to  claim 10 , wherein each memory cell further includes a bipolar transistor formed in the semiconductor substrate, a collector or an emitter of the bipolar transistor being connected to a corresponding one of the first regions, a base of the bipolar transistor being connected to the word line.  
     
     
         18 . The device according to  claim 10 , wherein each memory cell further includes a MOS transistor formed on the semiconductor substrate, a source or a drain of the MOS transistor being connected to a corresponding one of the first regions, a gate of the bipolar transistor being connected to the word line.  
     
     
         19 . The device according to  claim 10 , wherein the second region of each phase-change layer is in a crystalline state, and at least part of each first region of each phase-change layer assumes one of the crystalline state and an amorphous state in accordance with write data.