US2006128141A1PendingUtilityA1

Semiconductor device and method for fabricating the same

Assignee: MATSUSHITA ELECTRIC INDUSTRIAL CO LTDPriority: Feb 23, 2000Filed: Jan 26, 2006Published: Jun 15, 2006
Est. expiryFeb 23, 2020(expired)· nominal 20-yr term from priority
Inventors:Hiroshi Yuasa
H10P 95/00H10P 50/287H10P 14/6304H10W 20/495H10W 20/081H10W 20/076H10W 20/48H10W 20/47H10P 50/73
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Claims

Abstract

An insulating film is formed of a carbon-containing silicon dioxide film on a semiconductor substrate. In the insulating film, an interconnect groove is formed. A silicon dioxide layer with a density high enough to allow almost no oxygen to pass therethrough is formed on the bottom and side faces of the interconnect groove. And a metal interconnect is formed on the silicon dioxide layer inside the interconnect groove.

Claims

exact text as granted — not AI-modified
1 . A method for forming a semiconductor device, comprising the steps of: 
 a) forming an insulating film of a carbon-containing silicon oxide film over a substrate;    b) etching the insulating film using a resist pattern as a mask, thereby forming an interconnect groove in the insulating film;    c) performing an etching process, thereby removing a surface film of the resist pattern and forming a silicon oxide layer on an inner face of the interconnect groove,    d) removing the resist pattern; and    e) filling the interconnect groove with a metal film to form a metal interconnect.    
   
   
       2 . The method of  claim 1 , wherein the performing an etching process, thereby removing the surface film of the resist pattern and forming a silicon oxide layer on the inner face of the interconnect groove at the same time.  
   
   
       3 . The method of  claim 1 , wherein the etching process uses an etching gas containing oxygen.  
   
   
       4 . The method of  claim 1 , wherein the etching process is formed within plasma ambient at a pressure of 13.3 Pa or more.  
   
   
       5 . The method of  claim 1 , wherein the etching process is an anisotropic RIE process.  
   
   
       6 . The method of  claim 1 , further comprising the steps of removing the silicon oxide layer, existing on the inner face of the interconnect groove, after removing the resist pattern and before filling the interconnect groove with the metal film.  
   
   
       7 . The method of  claim 1 , wherein the silicon oxide layer has a thickness of 20 nm or less.  
   
   
       8 . The method of  claim 1 , wherein the silicon oxide layer has a density of 2.0 g/cm3 or more.  
   
   
       9 . The method of  claim 1 , wherein the metal interconnect is made up of a barrier metal layer and a main interconnect layer.

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