Method of removing etch residues

Abstract

Organic etch residues are often left within vias formed by etching through resist masks. Since the etch is designed to expose an underlying metal layer and is directional in order to produce vertical via sidewalls, the residue often incorporates metal. The present invention discloses a method of removing such etch residues while passivating exposed metal, including exposing the residue to ammonia. In the disclosed embodiment, ammonia and oxygen are mixed in a plasma step, such that the resist can be burned off at the same time as the residue treatment. The residue can thus be easily rinsed away.

1 . A method of cleaning a via in a partially fabricated integrated circuit, comprising: 
 providing a partially fabricated integrated circuit, the integrated circuit comprising a metal layer, a dielectric layer above the metal layer, and an organic resist layer above the dielectric layer, wherein an opening extends through the resist layer and dielectric layer to expose the metal layer; and    cleaning the opening by exposing the opening to a plasma that simultaneously removes the resist layer, wherein the plasma is formed from a gas comprising ammonia.    
   
   
       2 . The method of  claim 1 , wherein the gas further comprises oxygen.  
   
   
       3 . The method of  claim 2 , wherein the gas comprises at least about 25% ammonia.  
   
   
       4 . The method of  claim 3 , wherein the gas comprises at least about 50% ammonia.  
   
   
       5 . The method of  claim 1 , wherein exposing the opening to a plasma occurs at a temperature between about 100° and about 400° C.  
   
   
       6 . The method of  claim 1 , wherein the dielectric layer comprises an oxide.  
   
   
       7 . The method of  claim 1 , wherein providing the partially fabricated integrated circuit comprises etching a via in the dielectric layer, wherein etching the via is performed through an opening in the resist layer and wherein etching the via forms the opening extending through the resist layer and the anti-reflective coating.  
   
   
       8 . The method of  claim 7 , wherein etching the via comprises a plasma etch.  
   
   
       9 . The method of  claim 1 , further comprising depositing a conductive material into the opening after cleaning the opening.  
   
   
       10 . The method of  claim 1 , further comprising providing an anti-reflective coating between the metal layer and the dielectric layer.  
   
   
       11 . The method of  claim 1 , further comprising providing a residue in the opening, wherein cleaning the opening removes the residue.  
   
   
       12 . The method of  claim 11 , wherein the residue comprises a polymeric matrix including metal from the metal layer.  
   
   
       13 . The method of  claim 12 , wherein the residue further comprises material from the dielectric layer, the resist layer and from etchant used to form the opening.  
   
   
       14 . A method of forming and cleaning a void in a partially fabricated integrated circuit, comprising: 
 providing a partially fabricated integrated circuit having a resist layer with an aperture, the resist layer overlying a dielectric layer which overlies a metal layer;    forming a void which exposes the metal layer by etching the dielectric layer through the aperture, wherein etching forms a residue in the void; and    removing the residue by exposing the partially fabricated integrated circuit to a plasma formed from a gas comprising ammonia.    
   
   
       15 . The method of  claim 14 , wherein exposing the partially fabricated integrated circuit to the plasma removes the resist layer.  
   
   
       16 . The method of  claim 14 , wherein the gas comprises oxygen.  
   
   
       17 . The method of  claim 14 , wherein the gas comprises air.  
   
   
       18 . The method of  claim 14 , wherein the residue comprises metal from the metal layer.  
   
   
       19 . The method of  claim 14 , wherein forming the void comprises performing a directional etch.  
   
   
       20 . The method of  claim 19 , wherein forming the void comprises a reactive ion etch.  
   
   
       21 . The method of  claim 20 , wherein a radio frequency power is set to at least about 900 W during the reactive ion etch.  
   
   
       22 . The method of  claim 20 , wherein the reactive ion etch is magnetically enhanced.  
   
   
       23 . The method of  claim 14 , wherein forming the void comprises etching through a covering layer disposed between the metal layer and the dielectric layer.  
   
   
       24 . The method of  claim 23 , wherein the covering layer comprises an antireflection layer.  
   
   
       25 . The method of  claim 23 , wherein the metal covering layer comprises titanium nitride.  
   
   
       26 . The method of  claim 14 , further comprising rinsing the void after removing the resist layer and the residue.  
   
   
       27 . The method of  claim 26 , wherein rinsing the exposed void comprises dipping the integrated circuit into a dilute phosphoric acid bath.  
   
   
       28 . The method of  claim 26 , wherein rinsing the exposed void comprises exposing a void sidewall to deionized water.  
   
   
       29 . The method of  claim 26 , wherein rinsing the exposed void comprises exposing a void sidewall to isopropyl alcohol.