Method and system for monitoring embedded disk controller components

Abstract

A history module for monitoring plural components in an embedded disk controller with a first main processor operationally coupled to a first bus and a second processor operationally coupled to a second bus is provided. The history module includes an event control module that receives break point conditions that stops the history module from recording information of a component; and a first register that allows selection or-de-selection of certain components in the embedded disk controller. The first register can also store a trigger mode value, which specifies a number of entries that are made in history module buffer(s) after a break point condition is detected.

1 - 13 . (canceled)  
   
   
       14 . An embedded disk controller, comprising: 
 a first bus;    a first processor that communicates with said first bus;    a second bus;    a first device that communicates with one of said first and second buses;    a second processor that communicates with said second bus;    a history module that is located in the embedded disk controller, that communicates with the first bus and the second bus, and that at least one of monitors transaction information of said first device and masks transaction information of said first device based on setup information.    
   
   
       15 . The embedded disk controller of  claim 14  wherein the history module includes at least one storage device that stores the setup information.  
   
   
       16 . The embedded disk controller of  claim 15  further comprising a map of the at least one storage device.  
   
   
       17 . The embedded disk controller of  claim 14  wherein the setup information includes a break point condition value that is indicative of a break point condition and wherein the first processor determines the break point condition value.  
   
   
       18 . The embedded disk controller of  claim 17  wherein the history module stops recording transaction information based on the break point condition value.  
   
   
       19 . The embedded disk controller of  claim 18  wherein the setup information further includes a trigger mode field value and wherein the history module begins recording based on a number of entries between the break point value and the trigger mode value.  
   
   
       20 . The embedded disk controller of  claim 14  wherein the setup information includes a read mask field value and a write mask field value and wherein the history module stops recording at least one of read operations and write operations on at least one of the first bus and the second bus based on the read mask field value and the write mask field value.  
   
   
       21 . The embedded disk controller of  claim 14  wherein the setup information includes a masking field value and wherein the history module does not record transaction information of the first device based on the masking field value.  
   
   
       22 . The embedded disk controller of  claim 14  wherein the setup information includes an enable clock slam field value and wherein the history module generates a signal that stops clocks in the embedded disk controller based on the enable clock slam field value.  
   
   
       23 . The embedded disk controller of  claim 17  wherein the setup information includes a field value that one of enables and disables the break point condition value.  
   
   
       24 . The embedded disk controller of  claim 18  wherein the setup information includes a field value and wherein the history module selectively detects a break point condition based on the field value.  
   
   
       25 . The embedded disk controller of  claim 18  wherein the history module generates an interrupt of the first processor when a break point condition occurs.  
   
   
       26 . The embedded disk controller of  claim 18  wherein the history module includes a history stack pointer that indicates an oldest entry of transaction information in the history module.  
   
   
       27 . The embedded disk controller of  claim 26  wherein the first processor reads data from the history module based on the history stack pointer.  
   
   
       28 . The embedded disk controller of  claim 14  wherein the first processor is a main processor of the embedded disk controller and wherein the second processor is a digital signal processor of the embedded disk controller.