Structure of semiconductor substrate including test element group wiring

Abstract

A structure of test element group wiring includes, in addition to an electrode on a substrate including one or more layers of insulating films, and real wirings electrically connected to the electrode, includes dummy wirings electrically isolated from the electrode and having a portion of the same shape as the real wiring. The dummy wirings are disposed at a predetermined constant distance, adjacent to the real wirings or to each other, so that the wiring rate of the real wiring relaxes the concentration difference of patterns. The distance between the real wirings is sufficient to perform pattern analysis using the OBIRCH method.

1 - 6 . (canceled)  
   
   
       7 . A semiconductor substrate comprising: 
 a substrate including at least one layer of an insulating film,    a scribe line area dividing said substrate into a plurality of chip regions,    a plurality of semiconductor chips in respective chip regions defined by said scribe line area, and    a test element group (TEG) wiring in the scribe line area, wherein said TEG wiring includes: 
 an electrode on said substrate,  
 a real wiring electrically connected to said electrode, and  
 a plurality of dummy wirings electrically isolated from said electrode, disposed at constant intervals said real wiring, and having a portion of the same shape as said real wiring.  
   
   
   
       8 . The semiconductor substrate according to  claim 7 , wherein said dummy wirings include, when viewed from above, 
 inner dummy wirings disposed inside an area including said real wiring, and    outer dummy wirings disposed outside the area including said real wiring.    
   
   
       9 . The semiconductor substrate according to  claim 8 , wherein said inner dummy wirings have the same shape as said outer dummy wirings.  
   
   
       10 . The semiconductor substrate according to  claim 7 , wherein 
 said real wiring has at least two line portions substantially parallel to each other and at a predetermined interval, and    said dummy wirings are disposed in an area sandwiched between said line portions and parallel to said line portions at a predetermined interval.    
   
   
       11 . The semiconductor substrate according to  claim 7 , wherein said interval of said line portions is at least 3 μm.  
   
   
       12 . The semiconductor substrate according to  claim 7 , wherein the interval between one of said dummy wirings and one of (i) an adjacent dummy wiring and (ii) said real wiring is no more than 0.1 μm.