Prevention of data loss due to power failure

Abstract

In some embodiment, an arrangement is provided to prevent a loss of data in a memory due to a power failure for a computing system. When the power failure occurs, any pending memory write operations may be completed and dirty cache lines may be flushed back to the memory. Subsequently, the computing system may be put into a loss-prevention state, under which power may be turned off for all components in the computing system except the memory. The memory is powered by a battery pack which includes batteries and is in a self refresh state. When the power returns, applications and operating systems running in the computing system may resume what is left out when the power supply failure occurs, based at least in part on data retained in the memory. Other embodiments are described and claimed.

1 . A method for preventing data loss due to power failure in a computing system, comprising: 
 detecting a power failure in the computing system;    completing pending memory write operations and flushing dirty cache lines to a memory after the power failure is detected; and    putting the computing system in a loss-prevention state after the pending write operations are completed and the dirty cache lines are flushed to the memory.    
   
   
       2 . The method of  claim 1 , wherein the memory comprises volatile memory, the volatile memory including write-back caches in at least one of a processor and a disk drive.  
   
   
       3 . The method of  claim 1 , wherein the power failure comprises a failure of an alternating current (AC) power;  
   
   
       4 . The method of  claim 1 , further comprising triggering at least one of a state machine and a system management interrupt (SMI) to complete the pending memory write operations and to flush the dirty cache lines to the memory, after the power failure is detected.  
   
   
       5 . The method of  claim 1 , further comprising turning off power supply for all components in the computing system except the memory when the computing system is put in the loss-prevention state.  
   
   
       6 . The method of  claim 5 , further comprising restoring a status of the computing system just before the power failure occurs based on data preserved in the memory when power returns, the preserved data including hardware states just before the power failure occurs.  
   
   
       7 . The method of  claim 6 , wherein the hardware states are retained by a virtual machine monitor (VMM) in the memory, the VMM providing an operating system with information on hardware in the computing system.  
   
   
       8 . The method of  claim 7 , wherein the VMM restores the hardware states to states just before the power failure occurs and provides the restored hardware states to the operating system, when the power returns.  
   
   
       9 . The method of  claim 1 , wherein the loss-prevention state comprises a state under which data in the memory is refreshed using batteries, the batteries comprising at least two AA-sized batteries.  
   
   
       10 . The method of  claim 9 , further comprising: 
 detecting when the batteries need to be changed; and    sending an alert to a user of the computing system to change the batteries when the batteries need to be changed.    
   
   
       11 . An apparatus for preventing data loss due to power failure in a computing system, comprising: 
 a memory to store data accessible by components in the computing system;    power control logic to detect a power failure;    a power failure handling mechanism to complete pending memory write operations and to flush dirty cache lines to the memory, when informed by the power control logic of the power failure; and    a battery pack to supply power to the memory to refresh the data in the memory to prevent data loss in the memory, after the pending memory write operations are completed and the dirty cache lines are flushed to the memory.    
   
   
       12 . The apparatus of  claim 11 , wherein the memory comprises volatile memory, the volatile memory including write-back caches in at least one of a processor and a disk drive.  
   
   
       13 . The apparatus of  claim 11 , wherein the battery pack comprises at least two AA-sized batteries.  
   
   
       14 . The apparatus of  claim 11 , wherein the power failure comprises a failure of an alternating current (AC) power.  
   
   
       15 . The apparatus of  claim 11 , wherein the battery pack supplies power only to the memory to refresh the data in the memory, after the pending memory write operations are completed and the dirty cache lines are flushed to the memory.  
   
   
       16 . The apparatus of  claim 11 , further comprising: 
 a memory controller, coupled to the memory, to handle data traffic to and from the memory;    a first isolation circuitry to prevent current from the battery pack from flowing into a power supply when the battery pack is used to supply power to the memory after the power failure occurs, the power supply including an alternating current (AC) power supply;    a second isolation circuitry to prevent current from the power supply from flowing into the battery pack when the power supply is used to supply power to the memory and to prevent the battery pack from providing power to the memory when the power supply is present; and    a third isolation circuitry to prevent the battery pack from supplying power to the memory controller, when the battery pack is used to supply power to the memory.    
   
   
       17 . The apparatus of  claim 11 , further comprising a voltage regulator to regulate output power voltage provided by the battery pack.  
   
   
       18 . The apparatus of  claim 11 , further comprising: 
 a real-time clock well, the real-time clock well including a counter to count time during which the memory is powered by the battery pack; and    an alert sending mechanism, coupled to the real-time clock well, to send out a warning of replacing batteries in the battery pack when the counted time exceeds a pre-determined limit, the pre-determined limit set based on specifications of the batteries used in the battery pack.    
   
   
       19 . The apparatus of  claim 11 , wherein the power failure handling mechanism completes the pending write operations and flushes the dirty cache lines to the memory by using at least one of a state machine and at least one system management interrupt (SMI) handler.  
   
   
       20 . The apparatus of  claim 11 , wherein the power failure handling mechanism puts the computing system in a loss-prevention state after completing the pending write operations and flushing the dirty cache lines to the memory.  
   
   
       21 . The apparatus of  claim 20 , wherein the loss-prevention state comprises a state under which data in the memory is refreshed using power provided by the battery pack.  
   
   
       22 . The apparatus of  claim 20 , wherein the power failure handling mechanism turns off power to all components in the computing system except the memory, when the computing system is put in the loss-prevention state.  
   
   
       23 . A computing system, comprising: 
 at least one processor;    a power supply to supply power to components in the computing system;    a memory to store data accessible by the at least one processor; and    a battery pack to supply power to the memory to refresh the data in the memory after a power failure occurs.    
   
   
       24 . The computing system of  claim 23 , wherein the memory comprises volatile memory, the volatile memory including write-back caches in at least one of a processor and a disk drive.  
   
   
       25 . The computing system of  claim 23 , wherein the battery pack comprises at least two AA-sized batteries.  
   
   
       26 . The computing system of  claim 23 , wherein the power supply comprises an alternating current (AC) power supply.  
   
   
       27 . The computing system of  claim 23 , further comprising: 
 power control logic to detect the power failure; and    a power failure handling mechanism to complete pending memory write operations and to flush dirty cache lines to the memory by using at least one of a state machine and at least one system management interrupt (SMI) handler, when informed by the power control logic of the power failure.    
   
   
       28 . The computing system of  claim 27 , wherein the power failure handling mechanism puts the computing system in a loss-prevention state after completing the pending write operations and flushing the dirty cache lines to the memory, the loss-prevention state comprising a state under which data in the memory is refreshed using power provided by the battery pack.  
   
   
       29 . The computing system of  claim 27 , wherein the power failure handling mechanism turns off power to all components in the computing system except the memory, when the computing system is put in the loss-prevention state.  
   
   
       30 . The computing system of  claim 23 , further comprising: 
 a memory controller, coupled to the memory, to handle data traffic to and from the memory;    a voltage regulator to regulate output power voltage provided by the battery pack;    a first isolation circuitry to prevent current from the battery pack from flowing into the power supply when the battery pack is used to supply power to the memory after the power failure occurs;    a second isolation circuitry to prevent current from the power supply from flowing into the battery pack when the power supply is used to supply power to the memory and to prevent the battery pack from providing power to the memory when the power supply is present; and    a third isolation circuitry to prevent the battery pack from supplying power to the memory controller, when the battery pack is used to supply power to the memory.    
   
   
       31 . The computing system of  claim 23 , further comprising: 
 a real-time clock well, the real-time clock well including a counter to count time during which the memory is powered by the battery pack; and    an alert sending mechanism, coupled to the real-time clock well, to send out a warning of replacing batteries in the battery pack when the counted time exceeds a pre-determined limit, the pre-determined limit set based on specifications of the batteries used in the battery pack.    
   
   
       32 . The computing system of  claim 23 , further comprising a virtual machine monitor (VMM) to provide at least one operating system with information on hardware in the computing system, and to retain hardware states in the memory.  
   
   
       33 . The computing system of  claim 32 , wherein the VMM restores the hardware states to states just before the power failure occurs and provides the restored hardware states to the operating system, when the power returns.  
   
   
       34 . The computing system of  claim 32 , wherein the computing system resumes what processing is left when the power failure occurs based at least in part on data preserved in the memory during the power failure, the preserved data including the hardware states just before the power failure occurs.  
   
   
       35 . An article comprising a storage medium having stored thereon instructions that, when accessed by a processor result in the following: 
 detecting a power failure in the computing system;    completing pending memory write operations and flushing dirty cache lines to a memory after the power failure is detected; and    putting the computing system in a loss-prevention state after the pending write operations are completed and the dirty cache lines are flushed to the memory, the loss-prevention state comprises a state under which data in the memory is refreshed using batteries, the memory including volatile memory, the volatile memory including write-back caches in at least one of a processor and a disk drive.    
   
   
       36 . The article of  claim 35 , wherein the power failure comprises a failure of an alternating current (AC) power.  
   
   
       37 . The article of  claim 35 , wherein the instructions when accessed by the processor also result in: 
 triggering at least one of a state machine and a system management interrupt (SMI) to complete the pending memory write operations and to flush the dirty cache lines to the memory, after the power failure is detected; and    turning off power supply for all components in the computing system except the memory when the computing system is put in the loss-prevention state.    
   
   
       38 . The article of  claim 37 , wherein the instructions when accessed by the processor further result in restoring a status of the computing system just before the power failure occurs based on data preserved in the memory when power returns, the preserved data including hardware states just before the power failure occurs.  
   
   
       39 . The article of  claim 38 , wherein the hardware states are retained by a virtual machine monitor (VMM) in the memory, the VMM restoring the hardware states to states just before the power failure occurs and providing the restored hardware states to an operating system, when the power returns.