Thin film transistor, flat panel display including the thin film transistor, and method for manufacturing the thin film transistor and the flat panel display

Abstract

A thin film transistor having a transformed region that provides the same result as patterning a semiconductor layer, a flat panel display having the thin film transistor and a method for manufacturing the thin film transistor and the flat panel display are disclosed. The thin film structure includes a gate electrode, a source and a drain electrode, each insulated from the gate electrode and an organic semiconductor layer coupled to the source electrode and the drain electrode. The organic semiconductor layer includes the transformed region having a crystal structure distinguished from crystal structures of regions around the channel region.

1 . A thin film transistor, comprising: 
 a gate electrode;    a source electrode and a drain electrode, each insulated from the gate electrode; and    an organic semiconductor layer insulated from the gate electrode and coupled to the source electrode and the drain electrode,    wherein the organic semiconductor layer comprises a transformed region around at least a channel region, the transformed region having a crystal structure distinguished from other regions.    
     
     
         2 . The thin film transistor of  claim 1 , wherein the crystal size of the transformed region is smaller than the crystal size of the other regions.  
     
     
         3 . The thin film transistor of  claim 1 , wherein the transformed region has lower current mobility than the other regions.  
     
     
         4 . The thin film transistor of  claim 1 , wherein the transformed region is formed by emitting light on a predetermined region where the transformed region is formed.  
     
     
         5 . The thin film transistor of  claim 1 , wherein the transformed region is formed by performing a thermal process on a predetermined region where the transformed region is formed.  
     
     
         6 . The thin film transistor of  claim 1 , wherein the transformed region comprises a boundary having a closed curve shape surrounding at least the channel region.  
     
     
         7 . The thin film transistor of  claim 1 , wherein the transformed region comprises a boundary formed on at least one pair of substantially parallel lines where at least the channel region is located between the substantially parallel lines.  
     
     
         8 . The thin film transistor of  claim 1 , wherein the transformed region comprises a boundary substantially parallel to a line connecting the source region, the channel region and the drain region.  
     
     
         9 . The thin film transistor of  claim 1 , wherein an insulation layer is formed covering the gate electrode, and the organic semiconductor layer is formed on the insulation layer.  
     
     
         10 . The thin film transistor of  claim 1 , further comprising: 
 an insulation layer covering the gate electrode; wherein, the source electrode and drain electrode are each formed on the insulation layer;    a passivation layer covering the insulation layer, the source electrode and the drain electrode; wherein, the passivation layer has an opening over the source electrode or the drain electrode, wherein the organic semiconductor layer is formed on the passivation layer.    
     
     
         11 . The thin film transistor of  claim 1 , wherein the source electrode and drain electrode are each formed on a substrate and the organic semiconductor layer is formed on the substrate so as to cover the source electrode and drain electrode.  
     
     
         12 . The thin film transistor of  claim 1 , wherein the organic semiconductor layer is formed on a substrate, and the source electrode and the drain electrode are each formed on the organic semiconductor layer.  
     
     
         13 . The thin film transistor of  claim 1 , wherein the organic semiconductor layer comprises at least one of pentacene, tetracene, anthracene, naphthalene, alpha-6-thiophene, alpha-4-thiophene, perylene and its derivatives, rubrene and its derivatives, coronene and its derivatives, perylene tetracarboxylic diimide and its derivatives, perylene tetracarboxylic dianhydride and its derivates, oligonaphthalene and its derivatives, oligothiophene of alpha-5-thiophene and its derivatives, phthalocyanine including metal and its derivates, phthalocyanine not including metal and its derivates, naphthalene tetracarboxylic diimide and its derivatives, naphthalene tetracarboxylic dianhydride and its derivatives, pyromellitic dianhydride and its derivatives, pyromellitic diimide and its derivatives, conjugated polymer containing thiophene and its derivatives and polymer containing fluorene and its derivatives.  
     
     
         14 . A flat panel display, comprising: 
 a substrate;    at least one thin film transistor, each of which is formed on the substrate and comprises a gate electrode, a source electrode and a drain electrode, each insulated from the gate electrode and an organic semiconductor layer coupled to the source electrode and the drain electrode and insulated from the gate electrode; and    a pixel electrode electrically connected to at least one of the source and the drain electrodes of the thin film transistor,    wherein the organic semiconductor layer comprises a transformed region around at least the channel region of the organic semiconductor layer, wherein the transformed region has a crystal structure which differs from other regions of the organic semiconductor layer.    
     
     
         15 . The flat panel display of  claim 14 , wherein the crystal size of the transformed region is smaller than a crystal size of the other regions.  
     
     
         16 . The flat panel display of  claim 14 , wherein the transformed region has lower current mobility than the other regions.  
     
     
         17 . The flat panel display of  claim 14 , wherein the transformed region is formed by irradiating a predetermined region with light where the transformed region is formed.  
     
     
         18 . The flat panel display of  claim 14 , wherein the transformed region is formed by performing a thermal process on a predetermined region where the transformed region is to be formed.  
     
     
         19 . The flat panel display of  claim 14 , wherein the transformed region comprises a boundary having a closed curve shape surrounding at least the channel region.  
     
     
         20 . The flat panel display of  claim 14 , wherein the transformed region comprises a boundary formed on at least one pair of substantially parallel lines wherein at least the channel region is located between the substantially parallel lines.  
     
     
         21 . The flat panel display of  claim 14 , wherein the transformed region comprises a boundary substantially parallel to a line connecting to the source region, the channel region and the drain region.  
     
     
         22 . The flat panel display of  claim 14 , wherein an insulation layer is formed for covering the gate electrode and the organic semiconductor layer is formed on the insulation layer.  
     
     
         23 . The flat panel display of  claim 14 , further comprising: 
 an insulation layer covering the gate electrode; wherein, the source electrode and drain electrode are each formed on the insulation layer;    a passivation layer covering the insulation layer, the source electrode and the drain electrode, wherein the passivation layer has an opening above the source electrode or drain electrode; wherein,    the organic semiconductor layer is formed on the passivation layer.    
     
     
         24 . The flat panel display of  claim 14 , wherein the source electrode and drain electrode are each formed on a substrate and the organic semiconductor layer is formed on the substrate so as to cover the source electrode and drain electrode.  
     
     
         25 . The flat panel display of  claim 14 , wherein the organic semiconductor layer is formed on a substrate, and the source electrode and the drain electrode are each formed on the organic semiconductor layer.  
     
     
         26 . The flat panel display of  claim 14 , wherein the organic semiconductor layer comprises at least one of pentacene, tetracene, anthracene, naphthalene, alpha-6-thiophene, alpha-4-thiophene, perylene and its derivatives, rubrene and its derivatives, coronene and its derivatives, perylene tetracarboxylic diimide and its derivatives, perylene tetracarboxylic dianhydride and its derivates, a oligonaphthalene and its derivatives, oligothiophene of alpha-5-thiophene and its derivatives, phthalocyanine including metal and its derivates, phthalocyanine not including a metal and its derivates, naphthalene tetracarboxylic diimide and its derivatives, naphthalene tetracarboxylic dianhydride and its derivatives, pyromellitic dianhydride and its derivatives, pyromellitic diimide and its derivatives, conjugated polymer containing thiophene and its derivatives and polymer containing fluorene and its derivatives.  
     
     
         27 . A method of manufacturing a thin film transistor comprising a gate electrode, a source electrode and a drain electrode, each insulated from the gate electrode; and an organic semiconductor layer insulated from the gate electrode and coupled to the source and the drain electrodes, 
 the method comprising irradiating with light the area around at least a channel region of the organic semiconductor layer wherein the conductivity of the organic semiconductor layer is reduced.    
     
     
         28 . The method of  claim 27 , wherein the organic semiconductor layer is irradiated by a laser.  
     
     
         29 . The method of  claim 27 , wherein the organic semiconductor layer is irradiated with ultraviolet light.  
     
     
         30 . The method of  claim 27 , wherein the organic semiconductor layer comprises at least one of pentacene, tetracene, anthracene, naphthalene, alpha-6-thiophene, alpha-4-thiophene, perylene and its derivatives, rubrene and its derivatives, coronene and its derivatives, perylene tetracarboxylic diimide and its derivatives, perylene tetracarboxylic dianhydride and its derivates, a oligonaphthalene and its derivatives, oligothiophene of alpha-5-thiophene and its derivatives, phthalocyanine including a metal and its derivates, phthalocyanine not including a metal and its derivates, naphthalene tetracarboxylic diimide and its derivatives, naphthalene tetracarboxylic dianhydride and its derivatives, pyromellitic dianhydride and its derivatives, pyromellitic diimide and its derivatives, conjugate polymer containing thiophene and its derivatives and polymer containing fluorene and its derivatives.  
     
     
         31 . A method of manufacturing a thin film transistor comprising a gate electrode; a source electrode and a drain electrode, each insulated from the gate electrode; and an organic semiconductor layer insulated from the gate electrode and coupled to the source and drain electrodes, 
 the method comprises performing a thermal process on the organic semiconductor layer at least near a channel region of the organic semiconductor layer after forming the organic semiconductor layer, wherein the conductivity of the organic semiconductor layer is reduced.    
     
     
         32 . The method of  claim 31 , wherein the organic semiconductor layer comprises at least one of pentacene, tetracene, anthracene, naphthalene, alpha-6-thiophene, alpha-4-thiophene, perylene and its derivatives, rubrene and its derivatives, coronene and its derivatives, perylene tetracarboxylic diimide and its derivatives, perylene tetracarboxylic dianhydride and its derivates, oligonaphthalene and its derivatives, oligothiophene of alpha-5-thiophene and its derivatives, phthalocyanine including a metal and its derivates, phthalocyanine not including a metal and its derivates, naphthalene tetracarboxylic diimide and its derivatives, naphthalene tetracarboxylic dianhydride and its derivatives, pyromellitic dianhydride and its derivatives, pyromellitic diimide and its derivatives, conjugate polymer containing thiophene and its derivatives and polymer containing fluorene and its derivatives.  
     
     
         33 . A method of manufacturing a flat panel display, comprising: 
 forming a thin film transistor comprising a gate electrode formed on a substrate; a source electrode and a drain electrode, each insulated from the gate electrode; and an organic semiconductor layer insulated from the gate electrode and coupled to the source and drain electrodes; and    forming a pixel electrode electrically connected to one of the source and the drain electrodes of the thin film transistor,    the method comprises irradiating with light the area around at least a channel region of the organic semiconductor layer wherein the conductivity of the organic semiconductor layer is reduced.    
     
     
         34 . The method of  claim 33 , wherein the organic semiconductor layer is irradiated with a laser.  
     
     
         35 . The method of  claim 33 , wherein the organic semiconductor layer is irradiated with ultraviolet light.  
     
     
         36 . The method of  claim 33 , wherein the organic semiconductor layer comprises at least one of pentacene, tetracene, anthracene, naphthalene, alpha-6-thiophene, alpha-4-thiophene, perylene and its derivatives, rubrene and its derivatives, coronene and its derivatives, perylene tetracarboxylic diimide and its derivatives, perylene tetracarboxylic dianhydride and its derivates, oligonaphthalene and its derivatives, oligothiophene of alpha-5-thiophene and its derivatives, phthalocyanine including a metal and its derivates, phthalocyanine not including metal and its derivates, naphthalene tetracarboxylic diimide and its derivatives, naphthalene tetracarboxylic dianhydride and its derivatives, pyromellitic dianhydride and its derivatives, pyromellitic diimide and its derivatives, conjugate polymer containing thiophene and its derivatives and polymer containing fluorene and its derivatives.  
     
     
         37 . A method of manufacturing a flat panel display, comprising: 
 forming a thin film transistor comprising a gate electrode formed on a substrate, a source electrode and a drain electrode, each insulated from the gate electrode; and an organic semiconductor layer insulated from the gate electrode and coupled to the source and the drain electrodes; and    forming a pixel electrode electrically connected to one of the source and the drain electrodes of the thin film transistor,    the method comprises performing a thermal process on the organic semiconductor layer at least near a channel region of the organic semiconductor layer after forming the organic semiconductor layer, wherein the conductivity of the organic semiconductor layer is reduced.    
     
     
         38 . The method of  claim 37 , wherein the organic semiconductor layer comprises at least one of pentacene, tetracene, anthracene, naphthalene, alpha-6-thiophene, alpha-4-thiophene, perylene and its derivatives, rubrene and its derivatives, coronene and its derivatives, perylene tetracarboxylic diimide and its derivatives, perylene tetracarboxylic dianhydride and its derivates, oligonaphthalene and its derivatives, oligothiophene of alpha-5-thiophene and its derivatives, phthalocyanine including metal and its derivates, phthalocyanine not including metal and its derivates. naphthalene tetracarboxylic diimide and its derivatives, naphthalene tetracarboxylic dianhydride and its derivatives, pyromellitic dianhydride and its derivatives, pyromellitic diimide and its derivatives, conjugate polymer containing thiophene and its derivatives and polymer containing fluorene and its derivatives.