Memory mapped spin lock controller

Abstract

A method, in a computer system having a centralized spin lock controller arrangement, for managing a spin lock between a first processor and a second processor. The first processor holds the spin lock, the second processor contends for the spin lock, and the spin lock is implemented using a line of memory. The method includes invalidating a first private copy of the line that is held by the first processor. The method further includes providing a second private copy of the line to the second processor even before the first processor releases the spin lock, thereby preventing the second processor from requesting for a private copy of the line again while the spin lock is still held by the first processor.

1 . In a computer system having a centralized spin lock controller arrangement, a method for managing a spin lock between a first processor and a second processor, said first processor holding said spin lock, said second processor contending for said spin lock, said spin lock being implemented using a line of memory, comprising: 
 invalidating a first private copy of said line that is held by said first processor; and    providing a second private copy of said line to said second processor even before said first processor releases said spin lock, thereby preventing said second processor from requesting for a private copy of said line again while said spin lock is still held by said first processor.    
   
   
       2 . The method of  claim 1  further comprising: 
 queuing a request by said second processor for said spin lock into a request queue, said queuing said request resulting in said second processor being granted said spin lock after said spin lock is released by said first processor.    
   
   
       3 . The method of  claim 2  wherein said invalidating said first private copy of said line is performed using a test-and-set procedure.  
   
   
       4 . In a computer system having a centralized spin lock controller arrangement, a method for managing a spin lock among a plurality of processors, said spin lock being held by a first processor of said plurality of processors, said spin lock being implemented using a line of memory, comprising: 
 providing a first private copy of said line to said first processor; thereafter    permitting said first processor to write said private copy of said line in a cache of said first processor without signaling said centralized spin lock controller arrangement that said first processor is going to write to said private copy of said line if no other processor of said plurality of processors contends for said spin lock.    
   
   
       5 . The method of  claim 4  further comprising invalidating said first private copy of said line that is held by said first processor only if said spin lock is contended for by at least one processor other than said first processor before said first processor is finished with said private copy of said line.  
   
   
       6 . The method of  claim 4  further comprising: 
 receiving a request for said spin lock by a second processor of said plurality of processors;    invalidating said first private copy of said line that is held by said first processor responsive to said receiving said request; and    providing a second private copy of said line to said second processor even before said spin lock is released by said first processor.    
   
   
       7 . The method of  claim 6  further comprising: 
 queuing said request for said spin lock by said second processor into a request queue, said queuing said request resulting in said second processor obtaining said spin lock when said spin lock is released by said first processor.    
   
   
       8 . The method of  claim 4  wherein said first processor is configured to release said spin lock, when no other processor is contending for said spin lock, by writing a predefined value into said first private copy of said line without having to first request another private copy of said line.  
   
   
       9 . The method of  claim 7  wherein said predefined value is all zeros.  
   
   
       10 . The method of  claim 1  wherein said second processor is allowed to request over and over said spin lock while said spin lock is held by said first processor without consuming bus bandwidth of said computer system.  
   
   
       11 . In a computer system having a centralized spin lock controller arrangement, a method for managing a spin lock among a plurality of contending processors and a first processor, said first processor holding said spin lock, said plurality of contending processors contending for said spin lock, said spin lock being implemented using a line of memory, comprising: 
 invalidating a first private copy of said line that is held by said first processor; and    providing private copies of said line to said plurality of contending processors even before said first processor releases said spin lock, thereby preventing processors in said plurality of contending processors from requesting for a private copy of said line again while said spin lock is still held by said first processor.    
   
   
       12 . The method of  claim 11  further comprising: 
 queuing requests by said plurality of processors for said spin lock into a request queue, said queuing said requests resulting in said plurality of processors being granted said spin lock over time after said spin lock is released by said first processor.    
   
   
       13 . The method of  claim 11  wherein said invalidating said first private copy employs a test-and-set procedure.  
   
   
       14 . The method of  claim 11  wherein said invalidating said first private copy includes writing a predefined value into said first private copy without having to first request another private copy of said line when no other processor is contending for said spin lock.  
   
   
       15 . An article of manufacture comprising a program storage medium having computer readable code embodied therein, said computer readable code being configured to a spin lock among a plurality of processors in a computer having a centralized spin lock controller arrangement, said spin lock being implemented using a line of memory, comprising: 
 computer-readable code for providing a first private copy of said line to said first processor; thereafter    computer-readable code for permitting said first processor to write said private copy of said line in a cache of said first processor without signaling said centralized spin lock controller arrangement that said first processor is going to write to said private copy of said line if no other processor of said plurality of processors contends for said spin lock.    
   
   
       16 . The article of manufacture of  claim 15  further comprising computer-readable code for invalidating said first private copy of said line that is held by said first processor only if said spin lock is contended for by at least one processor other than said first processor before said first processor is finished with said private copy of said line.  
   
   
       17 . The article of manufacture of  claim 15  further comprising: 
 computer-readable code for receiving a request for said spin lock by a second processor of said plurality of processors;    computer-readable code for invalidating said first private copy of said line that is held by said first processor responsive to said receiving said request; and    computer-readable code for providing a second private copy of said line to said second processor even before said spin lock is released by said first processor.    
   
   
       18 . The article of manufacture of  claim 17  further comprising: 
 computer-readable code for queuing said request for said spin lock by said second processor into a request queue, said queuing said request resulting in said second processor obtaining said spin lock when said spin lock is released by said first processor.    
   
   
       19 . The article of manufacture of  claim 15  wherein said first processor is configured to release said spin lock, when no other processor is contending for said spin lock, by writing a predefined value into said first private copy of said line without having to first request another private copy of said line.  
   
   
       20 . The article of manufacture of  claim 18  wherein said predefined value is all zeros.