On chip power supply

Abstract

A technique, for drawing power from the external signal circuit to power on-chip elements for an integrated circuit diode (ICD), utilizes an integrated diode and capacitor. The capacitor is charged by the external applied voltage during the time the ICD blocks the external current flow. The charged capacitor then acts as a battery to power the on-chip circuits to provide active control for the ICD function. This ICD could be provided as a two terminal discrete diode, or integrated onto a larger IC. This same technique can be utilized for a “self powered” MOSFET IC (ICM), utilizing a low power logic signal to trigger an internal circuit which would provide a much larger gate drive than the logic signal could provide. This could also be provided as discrete three terminal components, or integrated into a larger IC.

1 - 41 . (canceled)  
   
   
       42 . A circuit comprising: 
 an integrated circuit including: 
 a capacitor;  
 a diode;  
 a field effect transistor having a source, a drain and a gate; and,  
 a control circuit;  
   the capacitor and the diode being connected in series between the source and drain with the diode being conductive to charge the capacitor when the transistor is turned off, the capacitor being coupled to and acting as the power supply for the control circuit, the control circuit having a gate control input and providing an output coupled to the gate of the field effect transistor to provide an enhanced gate control signal to the field effect transistor on both turn on and turn off of the field effect transistor responsive to the gate control input.    
   
   
       43 . The circuit of  claim 42  wherein the field effect transistor is an n-channel MOSFET.  
   
   
       44 . The circuit of  claim 42  wherein the field effect transistor is a p-channel MOSFET.  
   
   
       45 . The circuit of  claim 42  wherein the field effect transistor is an n-channel JFET.  
   
   
       46 . The circuit of  claim 42  wherein the field effect transistor is a p-channel JFET.  
   
   
       47 . The circuit of  claim 42  wherein the circuit is packaged as a three terminal device.  
   
   
       48 . The circuit of  claim 42  wherein the enhanced gate control signal to the field effect transistor is enhanced in voltage swing in comparison to the gate control input.  
   
   
       49 . The circuit of  claim 42  wherein the enhanced gate control signal to the field effect transistor is enhanced in current drive in comparison to the gate control input.  
   
   
       50 . The circuit of  claim 42  wherein the enhanced gate control signal to the field effect transistor is enhanced in speed of gate drive transition in comparison to the gate control input.  
   
   
       51 . A circuit comprising: 
 an integrated circuit including: 
 a capacitor;  
 a diode;  
 a field effect transistor having a source, a drain, a gate and a body connected to the source; and,  
 a control circuit;  
   the capacitor and the diode being connected in series between the source and drain with the diode being conductive to charge the capacitor with respect to the source when the transistor is turned off, the capacitor being coupled to and acting as the power supply for the control circuit, the control circuit having a gate control input and providing an output coupled to the gate of the field effect transistor to provide an enhanced gate control signal to the field effect transistor on both turn on and turn off of the field effect transistor responsive to the gate control input, the enhanced gate control signal being responsive to a voltage on the capacitor for field effect transistor turn on and to a voltage on the source for field effect transistor turn off.    
   
   
       52 . The circuit of  claim 51  wherein the enhanced gate control signal is coupled to the voltage on the capacitor when the field effect transistor is turned on, and is coupled to the source when the field effect transistor is turned off.  
   
   
       53 . The circuit of  claim 52  further comprised of a Zener diode coupled to limit the maximum voltage that may be applied from the capacitor to the gate.  
   
   
       54 . The circuit of  claim 53  wherein the control circuit includes a bistable circuit responsive to the gate control input.  
   
   
       55 . The circuit of  claim 51  wherein the control circuit includes a bistable circuit responsive to the gate control input.  
   
   
       56 . The circuit of  claim 51  wherein the field effect transistor is an n-channel MOSFET.  
   
   
       57 . The circuit of  claim 51  wherein the field effect transistor is a p-channel MOSFET.  
   
   
       58 . The circuit of  claim 51  wherein the field effect transistor is an n-channel JFET.  
   
   
       59 . The circuit of  claim 51  wherein the field effect transistor is a p-channel JFET.  
   
   
       60 . The circuit of  claim 51  wherein the circuit is packaged as a three terminal device.  
   
   
       61 . A method of enhancing a gate control signal input for a field effect transistor having a source, a drain and a gate and responsive to a gate control signal comprising: 
 coupling a capacitor and a diode in series between the source and drain, the capacitor being coupled to the source, to charge the capacitor from a source-drain voltage when the field effect transistor is turned off;    powering a gate control circuit by the voltage on the capacitor;    coupling the gate control signal to the gate control circuit;    when the gate control signal indicates the field effect transistor is to be turned on, causing the gate control circuit to couple the gate to the voltage on the capacitor; and,    when the gate control signal indicates the field effect transistor is to be turned off, causing the gate control circuit to couple the gate to the source.    
   
   
       62 . The method of  claim 61  wherein the gate control circuit includes a bistable circuit.  
   
   
       63 . The method of  claim 61  further comprised of limiting the maximum voltage on the capacitor that may be coupled to the gate.