Gate oxide protected I/O circuit

Abstract

An integrated circuit comprises a first input node and a second input node, an output node; a first output transistor of a first type and a second output transistor of a second type, and a first clamping transistor of the second type and a second clamping transistor of the second type. The first clamping transistor, the first output transistor, the second clamping transistor, and the second output transistor are coupled in series across a first power supply terminal and a second power supply terminal. The first input node is coupled to a gate of the first output transistor. The second input node is coupled to a gate of the second output transistor. The output node is coupled to a common node of the first output transistor and the second clamping transistor. A gate of the first clamping transistor is coupled to a first reference voltage. A gate of the second clamping transistor is coupled to a second reference voltage.

1 . An integrated circuit comprising: 
 a first input node and a second input node;    an output node;    a first output transistor of a first type and a second output transistor of a second type; and    a first clamping transistor of the second type and a second clamping transistor of the second type,    wherein the first type can be a PMOS or an NMOS and the second type can respectively be an NMOS or a PMOS, the first clamping transistor, the first output transistor, the second clamping transistor, and the second output transistor are coupled in series across a first power supply terminal and a second power supply terminal, the first input node is coupled to a gate of the first output transistor, the second input node is coupled to a gate of the second output transistor, the output node is coupled to a common node of the first output transistor and the second clamping transistor, a gate of the first clamping transistor is coupled to a first reference voltage, and a gate of the second clamping transistor is coupled to a second reference voltage.    
   
   
       2 . The circuit of  claim 1 , wherein the first input node and the second input node provide the same logic signal.  
   
   
       3 . The circuit of  claim 1 , wherein the first output transistor is a PMOS transistor and the second output transistor, the first clamping transistor, and the second clamping transistor are NMOS transistors.  
   
   
       4 . The circuit of  claim 3 , wherein the first reference voltage and the second reference voltage are lower than a voltage provided by the first power supply terminal and higher than a voltage provided by the second power supply terminal, the first reference voltage and the second reference voltage respectively remain substantially the same voltage values.  
   
   
       5 . The circuit of  claim 4 , wherein the first reference voltage is higher than the second reference voltage.  
   
   
       6 . The circuit of  claim 3 , wherein a substrate of the first clamping transistor is coupled to a common node of the first clamping transistor and the first output transistor.  
   
   
       7 . The circuit of  claim 3 , wherein 
 a voltage at the common node of the first clamping transistor and the first output transistor is not higher than the first reference voltage minus a threshold voltage of the first clamping transistor; and    a voltage at the common node of the second clamping transistor and the second output transistor is not higher than the second reference voltage minus a threshold voltage of the second clamping transistor.    
   
   
       8 . The circuit of  claim 3 , wherein 
 the first power supply terminal provides approximately 5V and the second power supply terminal provides approximately 0V.    
   
   
       9 . The circuit of  claim 1 , further comprising: 
 a level shifter coupled to output signals to the first input node and the second input node, the level shifter coupled to a third power supply terminal and a fourth power supply terminal.    
   
   
       10 . The circuit of  claim 9 , further comprising: 
 an internal circuit coupled to output signals to the level shifter, the internal circuit coupled to a fifth power supply terminal and a sixth power supply terminal.    
   
   
       11 . The circuit of  claim 9 , further comprising: 
 a power-up circuit to provide a voltage to the third power supply terminal; and    a detection circuit to detect a completion of a power-up stage.    
   
   
       12 . The circuit of  claim 11 , wherein 
 the power-up circuit comprises a resister, a power-up stage transistor, an active stage transistor, a switch transistor, a first protection circuit, and a third power supply node;    the resistor, the switch transistor, and the first protection circuit are coupled in series across the first power supply terminal and the second power supply terminal, a gate of the switch transistor coupled to the detection circuit to receive a switch signal;    a first end of the power-up stage transistor is coupled to the first power supply terminal, a second end of the power-up stage transistor is coupled to the third power supply node, a gate of the power-up stage transistor is coupled to a common node of the resistor and the switch transistor; and    a first end of the active stage transistor is coupled to the first power supply terminal, a second end of the active stage transistor is coupled to the third power supply node and the second end of the power-up transistor, a gate of the active stage transistor is coupled to the first reference voltage.    
   
   
       13 . The circuit of  claim 12 , wherein 
 the power-up transistor and the active stage transistor are NMOS transistors;    a substrate and the second end of the power-up stage transistor are coupled to each other; and    a substrate of the active stage transistor is coupled to the second power supply terminal.    
   
   
       14 . The circuit of  claim 12 , wherein 
 the first protection circuit comprises a first protection transistor and a second protection transistor coupled in series.    
   
   
       15 . The circuit of  claim 14 , wherein 
 the first protection transistor comprises an NMOS transistor and the second protection transistor comprises a PMOS transistor;    a drain of the first protection transistor is coupled to the switch transistor, a gate and the drain of the first protection transistor are coupled to each other, a source of the first protection transistor is coupled to a source of the second protection transistor, a substrate of the first protection transistor is coupled to the second power supply terminal; and    the source and a substrate of the second protection transistor are coupled to each other, a gate and a drain of the second protection transistor are coupled to each other, the drain of the second protection transistor is coupled to the second power supply terminal.    
   
   
       16 . The circuit of  claim 12 , further comprising: 
 a second protection circuit coupled to a common node of the resistor and the switch transistor.    
   
   
       17 . The circuit of  claim 16 , wherein 
 the second protection circuit comprises a third protection transistor and a fourth protection transistor coupled in series; and    a first end of the third protection transistor is coupled to a first power supply terminal, a second end of the third protection transistor is coupled to a first end of the fourth protection transistor, gates of the third protection transistor and the fourth protection transistor are coupled to the first reference voltage, a second end of the fourth protection transistor is coupled to the common node of the resistor and the switch transistor.    
   
   
       18 . The circuit of  claim 9 , wherein a voltage of the third power supply terminal is provided by coupling to the common node of the first clamping transistor and the first output transistor.  
   
   
       19 . The circuit of  claim 18 , further comprising: 
 a power-up circuit to provide an intermediate voltage;    a detection circuit to detect a completion of a power-up stage; and    a regulator to receive the intermediate voltage and to generate the first reference voltage and the second reference voltage; 
 wherein  
 the power-up circuit comprises a resister, a power-up stage transistor, an active stage transistor, a switch transistor, and a first protection circuit;  
 the resistor, the switch transistor, and the first protection circuit are coupled in series across the first power supply terminal and the second power supply terminal, a gate of the switch transistor coupled to the detection circuit to receive a switch signal;  
 a first end of the power-up stage transistor is coupled to the first power supply terminal, a second end of the power-up stage transistor is coupled to the regulator, a gate of the power-up stage transistor is coupled to a common node of the resistor and the switch transistor; and  
 a first end of the active stage transistor is coupled to the first power supply terminal, a second end of the active stage transistor is coupled to the regulator and the second end of the power-up transistor, a gate of the active stage transistor is coupled to the first reference voltage.  
   
   
   
       20 . The circuit of  claim 19 , further comprising: 
 a second protection circuit coupled to a common node of the resistor and the switch transistor, the second protection circuit comprising a third protection transistor and a fourth protection transistor coupled in series; 
 wherein  
 a first end of the third protection transistor is coupled to a first power supply terminal, a second end of the third protection transistor is coupled to a first end of the fourth protection transistor, gates of the third protection transistor and the fourth protection transistor are coupled to the first reference voltage, a second end of the fourth protection transistor is coupled to the common node of the resistor and the switch transistor.  
   
   
   
       21 . An integrated circuit comprising: 
 a first input node and a second input node;    an output node;    a first PMOS transistor; and    a first NMOS transistor, a second NMOS transistor, and a third NMOS transistor,    wherein the first NMOS transistor, the first PMOS transistor, the second NMOS transistor, and    the third NMOS transistor are coupled in series across a first power supply terminal and a second power supply terminal, the first input node is coupled to a gate of the first PMOS transistor, the second input node is coupled to a gate of the third NMOS transistor, the output node is coupled to a common node of the first PMOS transistor and the second NMOS transistor, a gate of the first NMOS transistor is coupled to a first reference voltage, a gate of the second NMOS transistor is coupled to a second reference voltage.    
   
   
       22 . The circuit of  claim 21 , wherein 
 a substrate of the first NMOS transistor is coupled to a source of the first PMOS transistor; and    the first reference voltage and the second reference voltage are lower than a voltage provided by the first power supply terminal and higher than a voltage provided by the second power supply terminal.    
   
   
       23 . The circuit of  claim 22 , wherein the first reference voltage is higher than the second reference voltage.