Scan driver for selectively performing progressive scanning and interlaced scanning and a display using the same

Abstract

A scan driver that selectively performs progressive scanning and interlaced scanning and a display using the same. The scan driver includes a shift register having a plurality of flip-flops arranged in series, an odd line selection unit having a plurality of NAND gates, and an even line selection unit having a plurality of NAND gates. In response to an odd line control signal and an even line control signal input to the odd line selection unit and the even line selection unit, respectively, the scan driver performs progressive scanning or interlaced scanning. The scan driver may also include a mode selection unit to selectively perform progressive scanning or interlaced scanning in response to a mode selection signal.

1 . A scan driver that selectively performs progressive scanning and interlaced scannling, comprising: 
 a shift register for receiving a start pulse and a clock signal and outputting data at intervals of a cycle of the clock signal;    an odd line selection unit for receiving an output signal of an odd-numbered flip-flop of the shift register and an odd line control signal and performing a logical operation on the received signals to generate an odd scan signal; and    an even line selection unit for receiving an output signal of an even-numbered flip-flop of the shift register and an even line control signal and performing a logical operation on the received signals to generate an even scan signal.    
     
     
         2 . The scan driver of  claim 1 , wherein each flip-flop comprises: 
 a first latch for storing input data, which is sampled in a low-level period of the clock signal, on a rising edge of the clock signal; and    a second latch for storing the stored data of the first latch, which is sampled in a high-level period of the clock signal, on a falling edge of the clock signal.    
     
     
         3 . The scan driver of  claim 2 , wherein the first latch comprises: 
 a first sampler for sampling an input signal in a low-level period of the clock signal; and    a first holder for holding an output signal of the first sampler in a high-level period of the clock signal.    
     
     
         4 . The scan driver of  claim 3 , wherein the second latch comprises: 
 a second sampler for sampling an output signal of the first holder in a high-level period of the clock signal; and    a second holder for holding an output signal of the second sampler in a low-level period of the clock signal.    
     
     
         5 . The scan driver of  claim 2 , wherein the odd line selection unit comprises a plurality of NAND gates, each NAND gate receiving an output signal of an odd-numbered flip-flop and the odd line control signal.  
     
     
         6 . The scan driver of  claim 5 , wherein the even line selection unit comprises a plurality of NAND gates, each NAND gate receiving an output signal of an even-numbered flip-flop and the even line control signal.  
     
     
         7 . The scan driver of  claim 6 , wherein the scan driver selectively performs the progressive scanning and the interlaced scanning according to levels of the even line control signal and the odd line control signal.  
     
     
         8 . The scan driver of  claim 7 , wherein the scan driver performs the progressive scanning when both the even line control signal and the odd line control signal are at a high level.  
     
     
         9 . The scan driver of  claim 8 , wherein the odd line selection unit and the even line selection unit invert the received output signals of the flip-flops.  
     
     
         10 . The scan driver of  claim 9 , wherein each of the even line control signal and the odd line control signal comprises a pulse-train-type signal that transitions to a low level during each cycle of the clock signal.  
     
     
         11 . The scan driver of  claim 7 , wherein when the interlaced scanning is performed, the NAND gates of the odd line selection unit invert the received output signals of the odd-numbered flip-flops during an odd field period corresponding to half of a frame period, and the NAND gates of the even line selection unit invert the received output signals of the even-numbered flip-flops during an even field period corresponding to the remaining half of the frame period.  
     
     
         12 . The scan driver of  claim 11 , wherein when the odd line control signal is at a high level and the even line control signal is at a low level, the odd line selection unit activates the odd scan signal during the odd field period.  
     
     
         13 . The scan driver of  claim 12 , wherein the odd line control signal comprises a pulse-train-type signal that transitions to a low level during each cycle of the clock signal during the odd field period.  
     
     
         14 . The scan driver of  claim 12 , wherein when the odd line control signal is at a low level and the even line control signal is at a high level, the even line selection unit activates the even scan signal during the even field period.  
     
     
         15 . The scan driver of  claim 14 , wherein the even line control signal comprises a pulse-train-type signal that transitions to a low level during each cycle of the clock signal during the even field period.  
     
     
         16 . A display, comprising: 
 a pixel array including a plurality of pixels;    a scan driver for transmitting a scan signal and an emission control signal to the pixel array and selectively performing progressive scanning and interlaced scanning; and    a data driver for transmitting data to a pixel selected by the scan signal of the scan driver,    wherein the scan driver comprises:    a shift register for receiving a start pulse and a clock signal and outputting data at intervals of a cycle of the clock signal;    an odd line selection unit for receiving an output signal of an odd-numbered flip-flop of the shift register and an odd line control signal and performing a logical operation on the received signals to generate an odd scan signal; and    an even line selection unit for receiving an output signal of an even-numbered flip-flop of the shift register and an even line control signal and performing a logical operation on the received signals to generate an even scan signal.    
     
     
         17 . The display of  claim 16 , wherein each flip-flop comprises: 
 a first latch for storing input data, which is sampled in a low-level period of the clock signal, on a rising edge of the clock signal; and    a second latch for storing the stored data of the first latch, which is sampled in a high-level period of the clock signal, on a falling edge of the clock signal.    
     
     
         18 . The display of  claim 17 , wherein the first latch comprises: 
 a first sampler for sampling an input signal in a low-level period of the clock signal; and    a first holder for holding an output signal of the first sampler in a high-level period of the clock signal.    
     
     
         19 . The display of  claim 18 , wherein the second latch comprises: 
 a second sampler for sampling an output signal of the first holder in a high-level period of the clock signal; and    a second holder for holding an output signal of the second sampler in a low-level period of the clock signal.    
     
     
         20 . The display of  claim 17 , wherein the odd line selection unit comprises a plurality of NAND gates, each NAND gate receiving an output signal of an odd-numbered flip-flop and the odd line control signal.  
     
     
         21 . The display of  claim 20 , wherein the even line selection unit comprises a plurality of NAND gates, each NAND gate receiving an output signal of an even-numbered flip-flop and the even line control signal.  
     
     
         22 . The display of  claim 21 , wherein the scan driver selectively performs the progressive scanning and the interlaced scanning according to levels of the even line control signal and the odd line control signal.  
     
     
         23 . The display of  claim 22 , wherein the scan driver performs the progressive scanning when both the even line control signal and the odd line control signal are at a high level.  
     
     
         24 . The display of  claim 23 , wherein each of the even line control signal and the odd line control signal comprises a pulse-train-type signal that transitions to a low level during each cycle of the clock signal.  
     
     
         25 . The display of  claim 22 , wherein when the odd line control signal is at a high level and the even line control signal is at a low level, the odd line selection unit activates the odd scan signal during an odd field period corresponding to half of a frame period, and 
 wherein when the odd line control signal is at a low level and the even line control signal is at a high level, the even line selection unit activates the even scan signal during an even field period corresponding to the remaining half of the frame period.    
     
     
         26 . The display of  claim 25 , wherein the odd line control signal comprises a pulse-train-type signal that transitions to a low level during each cycle of the clock signal during the odd field period, and 
 the even line control signal comprises a pulse-train-type signal that transitions to a low level during each cycle of the clock signal during the even field period.    
     
     
         27 . The display of  claim 16 , wherein the display is an organic electroluminescent display, a liquid crystal display, or a plasma display panel.  
     
     
         28 . A scan driver that selectively performs progressive scanning and interlaced scanning, comprising: 
 a shift register for receiving a start pulse and a clock signal and outputting data at intervals of half of a cycle of the clock signal;    a mode selection unit for receiving an output signal of a flip-flop of the shift register and performing a logical operation on the output signal of the flip-flop in response to a mode selection signal;    an odd line selection unit for selecting an output signal of an odd-numbered flip-flop or an output signal of the mode selection unit in response to an odd line control signal; and    an even line selection unit for selecting an output signal of an even-numbered flip-flop or the output signal of the mode selection unit in response to an even line control signal.    
     
     
         29 . The scan driver of  claim 28 , wherein: 
 the shift register comprises a plurality of flip-flops that are connected in series;    odd-numbered flip-flops of the shift register sample an input signal and output the sampled input signal on a rising edge of the clock signal; and    even-numbered flip-flops of the shift register sample an input signal and output the sampled input signal on a falling edge of the clock signal.    
     
     
         30 . The scan driver of  claim 29 , wherein each odd-numbered flip-flop comprises: 
 a first sampler for sampling the input signal in a high-level period of the clock signal; and    a first holder for holding an output signal of the first sampler in a low-level period of the clock signal.    
     
     
         31 . The scan driver of  claim 30 , wherein each even-numbered flip-flop comprises: 
 a second sampler for sampling the input signal in a low-level period of the clock signal; and    a second holder for holding an output signal of the second sampler in a high-level period of the clock signal.    
     
     
         32 . The scan driver of  claim 28 , wherein the mode selection unit comprises: 
 a NOR gate for receiving the output signal of the odd-numbered flip-flop and the output signal of the even-numbered flip-flop, the even-numbered flip-flop being adjacent to the odd-numbered flip-flop; and    a NAND gate for receiving an output signal of the NOR gate and the mode selection signal.    
     
     
         33 . The scan driver of  claim 32 , wherein the mode selection unit performs a logical OR operation on the output signal of the odd-numbered flip-flop and the output signal of the even-numbered flip-flop during the progressive scanning, and 
 the mode selection unit masks the output signal of the odd-numbered flip-flop and the output signal of the even-numbered flip-flop by outputting a high-level signal during the interlaced scanning.    
     
     
         34 . The scan driver of  claim 28 , wherein the odd line selection unit comprises: 
 a first NAND gate for receiving the output signal of the odd-numbered flip-flop and the odd line control signal;    a second NAND gate for receiving the output signal of the mode selection unit corresponding to the mode selection signal and the output signal of the odd-numbered flip-flop and an inverted signal of the odd line control signal; and    a third NAND gate for receiving an output signal of the first NAND gate and an output signal of the second NAND gate.    
     
     
         35 . The scan driver of  claim 34 , wherein when the odd line control signal is at a high level, the odd line selection unit selects the output signal of the odd-numbered flip-flop, and 
 when the odd line control signal is at a low level, the odd line selection unit selects the output signal of the mode selection unit corresponding to the mode selection signal and the output signal of the odd-numbered flip-flop.    
     
     
         36 . The scan driver of  claim 35 , wherein the even line selection unit includes: 
 a fourth NAND gate for receiving the output signal of the even-numbered flip-flop and the even line control signal;    a fifth NAND gate for receiving the output signal of the mode selection unit corresponding to the mode selection signal and the output signal of the even-numbered flip-flop and an inverted signal of the even line control signal; and    a sixth NAND gate for receiving an output signal of the fourth NAND gate and an output signal of the fifth NAND gate.    
     
     
         37 . The scan driver of  claim 36 , wherein when the even line control signal is at a high level, the even line selection unit selects the output signal of the even-numbered flip-flop, and 
 when the even line control signal is at a low level, the even line selection unit selects the output signal of the mode selection unit corresponding to the mode selection signal and the output signal of the even-numbered flip-flop.    
     
     
         38 . A scan driver that selectively performs progressive scanning and interlaced scanning, comprising: 
 a shift register including a plurality of flip-flops connected in series, wherein odd-numbered flip-flops sample an input signal and output the sampled signal on a rising edge of a clock signal, and even-numbered flip-flops sample an input signal and output the sampled signal on a falling edge of the clock signal;    a mode selection unit for performing a logical OR operation on output signals of adjacent flip-flops or masking the output signals of the flip-flops in response to a mode selection signal;    an odd line selection unit for selecting an output signal of an odd-numbered flip-flop or an output signal of the mode selection unit in response to an odd line control signal; and    an even line selection unit for selecting an output signal of an even-numbered flip-flop or the output signal of the mode selection unit in response to an even line control signal.    
     
     
         39 . The scan driver of  claim 38 , wherein each odd-numbered flip-flop comprises: 
 a first sampler for sampling the input signal in a high-level period of the clock signal; and    a first holder for holding an output signal of the first sampler in a low-level period of the clock signal.    
     
     
         40 . The scan driver of  claim 39 , wherein each even-numbered flip-flop comprises: 
 a second sampler for sampling the input signal in a low-level period of the clock signal; and    a second holder for holding an output signal of the second sampler in a high-level period of the clock signal.    
     
     
         41 . The scan driver of  claim 38 , wherein the mode selection unit performs the logical OR operation on the output signals of the adjacent flip-flops when the mode selection signal requires the progressive scanning and masks the output signals of the flip-flops when the mode selection signal requires the interlaced scanning.  
     
     
         42 . The scan driver of  claim 41 , wherein during the progressive scanning, each of the odd line selection unit and the even line selection unit selects a result of the logical OR operation of the mode selection unit.  
     
     
         43 . The scan driver of  claim 41 , wherein during the interlaced scanning, the odd line selection unit selects the output signal of the odd-numbered flip-flop during an odd field period corresponding to half of a frame period and the even line selection unit selects the masked output signal of the mode selection unit.  
     
     
         44 . The scan driver of  claim 43 , wherein during an even field period corresponding to the remaining half of the frame period, the odd line selection unit selects the masked output signal of the mode selection unit and the even line selection unit selects the output signal of the even-numbered flip-flop.