Solid state disk controller apparatus

Abstract

A solid state disk controller apparatus comprises a first port; a second port having a plurality of channels; a central processing unit connected to a CPU bus; a buffer memory configured to store data to be transferred from the second port to the first port and from the first port to the second port; a buffer controller/arbiter block connected to the CPU bus and configured to control read and write operations of the buffer memory based on a control of the central processing unit; a first data transfer block connected between the first port and the buffer controller/arbiter block and configured to transfer data to be stored/read in/from the buffer memory bypassing the CPU bus; and a second data transfer block connected between the second port and the buffer controller/arbiter block and configured to transfer data to be stored/read in/from the buffer memory bypassing the CPU bus.

1 . A solid state disk controller apparatus comprising: 
 a first port:    a second port having a plurality of channels;    a central processing unit connected to a CPU bus;    a buffer memory configured to store data to be transferred from or to one of the first port and the second port;    a buffer controller/arbiter block connected to the CPU bus and configured to control read and write operations of the buffer memory based on a control of the central processing unit;    a first data transfer block connected between the first port and the buffer controller/arbiter block and configured to transfer data to be stored/read in/from the buffer memory in parallel to the CPU bus; and    a second data transfer block connected between the second port and the buffer controller/arbiter block and configured to transfer data to be stored/read in/from the buffer memory in parallel to the CPU bus.    
   
   
       2 . The solid state disk controller apparatus of  claim 1 , wherein the first data transfer block comprises: 
 a host interface control block connected to the CPU bus and configured to interface with an external host through the first port according to a control of the central processing unit; and    a first FIFO configured to provide a data transfer path between the host interface control block and the buffer controller/arbiter block bypassing the CPU bus.    
   
   
       3 . The solid state disk controller apparatus of  claim 2 , wherein the first port comprises: 
 a first channel connected to an external host of a serial ATA interface type;    a second channel connected to an external host of a parallel ATA interface type;    a conversion block configured to convert data to be input through the first channel into a serial ATA format and data to be output through the first channel into a parallel ATA format; and    a multiplexer configured to transfer data from the first channel or from the conversion block to the host interface control block, the multiplexer transferring data from the host interface block to either one of the second channel and the conversion block.    
   
   
       4 . The solid state disk controller apparatus of  claim 3 , wherein the first port is configured such that data from the first channel is directly transferred to the host interface control block and such that data from the host interface control block is directly transferred to the external host of the serial ATA interface type through the first channel.  
   
   
       5 . The solid state disk controller apparatus of  claim 1 , wherein the second data transfer block comprises: 
 a plurality of second FIFOs corresponding to the channels of the second port, respectively; and    a memory interface control block connected to the CPU bus and configured to interface with semiconductor memories through the second port,    wherein the plurality of second FIFOs are configured to provide data transfer paths between the memory interface control block and the buffer controller/arbiter block bypassing the CPU bus.    
   
   
       6 . The solid state disk controller apparatus of  claim 5 , further comprising a plurality of ECC blocks connected to the second FIFOs respectively, the plurality of ECC blocks configured to detect errors of data transferred through the second FIFOs and to generate error correction codes of data transferred to the semiconductor memories.  
   
   
       7 . The solid state disk controller apparatus of  claim 6 , wherein when an error is detected from data transferred through corresponding FIFOs, the ECC blocks are configured to correct erroneous data without interference of the central processing unit.  
   
   
       8 . The solid state disk controller apparatus of  claim 1 , wherein each of the channels of the second port is connected with a plurality of non-volatile memories.  
   
   
       9 . The solid state disk controller apparatus of  claim 8 , wherein the non-volatile memories connected to each channel of the second port are comprised of a non-volatile memory having the same type.  
   
   
       10 . The solid state disk controller apparatus of  claim 8 , wherein the same types of non-volatile memories are connected to each channel of the second port.  
   
   
       11 . The solid state disk controller apparatus of  claim 8 , wherein different types of non-volatile memories are connected to each channel of the second port.  
   
   
       12 . The solid state disk controller apparatus of  claim 8 , wherein the second data transfer block is configured to detect types of non-volatile memories connected to the channels of the second port at power-up and to control read and write operations of the non-volatile memories of each channel according to the detected result.  
   
   
       13 . The solid state disk controller apparatus of  claim 5 , wherein the second data transfer block is configured to control read and write operations of the semiconductor memories connected to the channels of the second port, based on either one of a hardware and software interleave protocol when read and write operations are requested to the channels of the second port.  
   
   
       14 . The solid state disk controller apparatus of  claim 5 , wherein the buffer controller/arbiter block is configured to process data in a round-robin manner when the first and second FIFOs request data process operations.  
   
   
       15 . The solid state disk controller apparatus of  claim 5 , wherein the memory interface control block comprises: 
 a control logic configured to generate a first clock signal to be transferred to a semiconductor memory through the second port, the semiconductor memory outputting data in synchronization with the first clock signal;    a delay circuit configured to delay the first clock signal and generate a second clock signal; and    a data fetch register configured to fetch the data from the semiconductor memory in synchronization with the second clock signal.    
   
   
       16 . The solid state disk controller apparatus of  claim 15 , wherein a delay time of the delay circuit is determined by delay information from an exterior source.  
   
   
       17 . The solid state disk controller apparatus of  claim 15 , wherein the memory interface control block further comprises a register for storing delay information that is used to determine a delay time of the delay circuit.  
   
   
       18 . A solid state disk controller apparatus comprises: 
 a first port;    a second port having a plurality of channels;    a central processing unit connected to a CPU bus;    a buffer memory configured to store data to be transferred from the second port to the first port or from the first port to the second port;    a host interface control block connected to the first port and the CPU bus and configured to interface with an external host according to a control of the central processing unit;    a buffer controller/arbiter block connected to the CPU bus and configured to control the buffer memory according to a control of the central processing unit;    a first FIFO configured to provide a data transfer path between the host interface control block and the buffer controller/arbiter block;    a memory interface control block connected to the second port and the CPU bus and configured to interface with non-volatile memories according to a control of the central processing unit; and    a plurality of second FIFOs configured to provide data transfer paths between the memory interface control block and the buffer controller/arbiter block.    
   
   
       19 . The solid state disk controller apparatus of  claim 18 , further comprising a plurality of ECC blocks connected to the second FIFOs respectively, the plurality of ECC blocks configured to detect errors of data transferred through corresponding second FIFOs and to generate error correction codes of data transferred to the non-volatile memories.  
   
   
       20 . The solid state disk controller apparatus of  claim 19 , wherein when an error is detected from data transferred through corresponding second FIFOs, the ECC blocks are configured to correct erroneous data without interference of the central processing unit.  
   
   
       21 . The solid state disk controller apparatus of  claim 18 , wherein non-volatile memories connected to each channel of the second port are comprised of non-volatile memories having the same types with each other.  
   
   
       22 . The solid state disk controller apparatus of  claim 21 , wherein the same types of non-volatile memories are connected to each channel of the second port.  
   
   
       23 . The solid state disk controller apparatus of  claim 18 , wherein different types of non-volatile memories are connected to each channel of the second port.  
   
   
       24 . The solid state disk controller apparatus of  claim 18 , wherein the memory interface control block is configured to detect types of non-volatile memories connected to the channels of the second port at power-up and to control read and write operations of the non-volatile memories of each channel according to the detected result.  
   
   
       25 . The solid state disk controller apparatus of  claim 18 , wherein the memory interface control block is configured to control read and write operations of the non-volatile memories connected to the channels of the second port, based on either one of a hardware and software interleave protocol when read and write operations are requested to the channels of the second port.  
   
   
       26 . The solid state disk controller apparatus of  claim 18 , wherein the buffer controller/arbiter block is configured to process data in a round-robin manner when the first and second FIFOs request data process operations.  
   
   
       27 . The solid state disk controller apparatus of  claim 18 , wherein the memory interface control block comprises: 
 a control logic configured to generate a first clock signal to be transferred to a semiconductor memory through the second port, the semiconductor memory outputting data in synchronization with the first clock signal;    a delay circuit configured to delay the first clock signal and generate a second clock signal; and    a data fetch register configured to fetch the data from the semiconductor memory in synchronization with the second clock signal.    
   
   
       28 . The solid state disk controller apparatus of  claim 27 , wherein a delay time of the delay circuit is determined by delay information from an exterior.  
   
   
       29 . The solid state disk controller apparatus of  claim 27 , wherein the memory interface control block further comprises a register for storing delay information that is used to determine a delay time of the delay circuit.  
   
   
       30 . A method of operation of a solid disk controller having a first port, a second port having a plurality of channels, a central processing unit connected to a CPU bus, a buffer memory configured to store data, and a buffer controller/arbiter connected to the CPU bus and configured to control read and write operations of the buffer memory under control of the central processing unit, the method comprising: 
 transferring data to be stored/read in/from in the buffer memory between the buffer memory and the first port bypassing the CPU bus; and    transferring data to be stored/read in/from in the buffer memory between the buffer memory and the second port bypassing the CPU bus.