System and method for reducing unnecessary cache operations

Abstract

A system and method for cache management in a data processing system. The data processing system includes a processor and a memory hierarchy. The memory hierarchy includes at least an upper memory cache, at least a lower memory cache, and a write-back data structure. In response to replacing data from the upper memory cache, the upper memory cache examines the write-back data structure to determine whether or not the data is present in the lower memory cache. If the data is present in the lower memory cache, the data is replaced in the upper memory cache without casting out the data to the lower memory cache.

1 . A method for cache management in a data processing system, wherein said data processing system includes a processor and a memory hierarchy, wherein said memory hierarchy includes at least an upper memory cache, at least a lower memory cache, and a write-back data structure, said method comprising: 
 in response to replacing data from said upper memory cache, examining said write-back data structure to determine whether or not said data is present in said lower memory cache; and    if said data is present in said lower memory cache, replacing said data in said upper memory cache without casting out said data to said lower memory cache.    
   
   
       2 . The method in  claim 1 , further comprising: 
 determining whether or not write-back data in said write-back data structure is utilized to determine whether or not said data is to be replaced in said upper memory cache; and    in response to determining said write-back data is not utilized, utilizing a least-recently used algorithm to determine whether or not to replace said data.    
   
   
       3 . The method in  claim 1 , further comprising: 
 in response to determining said data is to be replaced, placing said data in a write-back queue;    writing said data to said lower memory cache;    determining whether or not said data had been modified in said upper memory cache;    in response to determining said data had been modified in said upper memory cache, determining whether or not said data is present in said lower memory cache;    in response to determining said data is present in said lower memory cache, issuing a message to said upper memory cache indicating said data is present in said lower memory cache; and    in response to receiving said message, updating said write-back data structure.    
   
   
       4 . A computer program product, comprising: 
 code when executed emulates a data processing system, said data processing system include a first processing unit, second processing unit and a write-back data structure, said first processing unit, in response to replacing data from first processing unit, examining said write-back data structure to determine whether or not said data is present in said second processing unit; and    code when executed emulates said first processing unit replacing said data in said first processing unit without casting out said data to said second processing unit, if said data is present in said second processing unit.    
   
   
       5 . The computer program product in  claim 4 , further comprising: 
 code when executed emulates said data processing system determining whether or not write-back data in said write-back data structure is utilized to determine whether or not said data is to be replaced in said first processing unit; and    code when executed emulates said data processing system utilizing at least-recently used algorithm to determine whether or not to replace said data, in response to determining said write-back data is not utilized.    
   
   
       6 . The computer program product in  claim 4 , further comprising: 
 code when executed emulates said data processing system placing said data in a write-back queue, in response to determining said data is to be replaced;    code when executed emulates said data processing system writing said data to said second processing unit;    code when executed emulates said data processing system determining whether or not said data had been modified in said first processing unit; and    code when executed emulates said data processing system issuing a message to said first processing unit indicating said data is present in said second processing unit, in response to determining said data is present in said second processing unit.    
   
   
       7 . A processor, comprising: 
 a processor core;    a memory hierarchy, coupled to said processor core, said memory hierarchy further including an upper memory cache and a lower memory cache; and    a write-back data structure, coupled to said memory hierarchy, wherein said upper memory cache examines said write-back data structure to determine whether or not data is present in said lower memory cache, in response to replacing said data from said upper memory cache, and if said data is present in said lower memory cache, replacing said data in said upper memory cache without casting out said data to said lower memory cache.    
   
   
       8 . The processor in  claim 7 , said processor core further comprises: 
 a circuit to determine whether or not write-back data in said write-back data structure is utilized to determine whether or not said data is replaced in said upper memory cache; and    a circuit utilizing a least-recently used algorithm to determine whether or not to replace said data, in response to determining said write-back data is not utilized.    
   
   
       9 . The processor in  claim 7 , further comprising: 
 a write-back queue for queuing data once said processor core determines said data is to be replaced;    a first flag, included in said data, to indicated whether or not said data had been modified in said upper memory cache;    a second flag, included in an entry in said write-back data structure, indicating said data is present in said lower memory cache; and    a message generator for issuing a message to said upper memory cache is present in said lower memory cache.    
   
   
       10 . A data processing system, comprising: 
 a plurality of processors, in accordance with  claim 7;     a memory; and    an interconnect coupling said memory and said plurality of processors.    
   
   
       11 . The data processing system in  claim 10 , wherein said plurality of processors further comprise: 
 a circuit to determine whether or not write-back data in said write-back data structure is utilized to determine whether or not said data is replaced in said upper memory cache; and    a circuit utilizing a least-recently used algorithm to determine whether or not to replace said data, in response to determining said write-back data is not utilized.    
   
   
       12 . The data processing system in  claim 10 , further comprising: 
 a write-back queue for queuing data once said processor core determines said data is to be replaced;    a first flag, included in said data, to indicate whether or not said data had been modified in said upper memory cache;    a second flag, included in an entry in said write-back data structure, indicating said data is present in said lower memory cache; and    a message generator for issuing a message to said upper memory cache is present in said lower memory cache.    
   
   
       13 . A multi-chip module, with a plurality of processors in accordance with  claim 7 , wherein said plurality of processors further comprise: 
 a circuit to determine whether or not write-back data in said write-back data structure is utilized to determine whether or not said data is replaced in said upper memory cache; and    a circuit utilizing a least-recently used algorithm to determine whether or not to replace said data, in response to determining said write-back data is not utilized.    
   
   
       14 . The multi-chip module in  claim 13 , further comprising: 
 a write-back queue for queuing data once said processor core determines said data is to be replaced;    a first flag, included in said data, to indicate whether or not said data had been modified in said upper memory cache;    a second flag, included in an entry in said write-back data structure, indicating said data is present in said lower memory cache; and    a message generator for issuing a message to said upper memory cache is present in said lower memory cache.