Processor architecture

Abstract

A LIW processor comprises multiple execution units. The multiple execution units of the processor are divided into groups, and an input instruction word can contain instructions for one execution unit in each of the groups. The processor is optimised for use in signal processing operations, in that the multiple execution units of the processor are divided into groups which do not place significant restrictions on the desirable uses of the processor, because it has been determined that, in signal processing applications, it is not usually necessary for certain execution units to operate simultaneously. These execution units can therefore be grouped together, in such a way that only one of them can operate at a particular time, without significantly impacting on the operation of the device. An array is formed from multiple interconnected processors of this type.

1 . A long instruction word processor comprising a plurality of execution units; and 
 means for decoding instruction words containing sub-instructions, wherein: 
 said execution units are divided into a plurality of groups with each of said groups containing at least one execution unit,  
 a single instruction word contains a sub-instruction for one of said execution units in each of said groups, and  
 a single instruction word contains a respective sub-instruction for a respective execution unit in at least one of said plurality of groups.  
   
   
   
       2 . The processor of  claim 1 , further comprising: 
 an instruction memory having a fixed width, wherein a length of an instruction word depends on the number of sub-instructions in said instruction word.    
   
   
       3 . The processor of  claim 2 , wherein the fixed width of the instruction memory defines rows of said instruction memory and the means for decoding instruction words comprises means for decoding instruction words which cross row boundaries of said instruction memory.  
   
   
       4 . The processor of  claim 1 , wherein a first of said plurality of groups comprises a first arithmetic logic unit and a second of said plurality of groups comprises a communications unit, said communications unit being adapted for transferring data from an incoming data bus of said processor and for transferring data to an outgoing data bus of said processor.  
   
   
       5 . The processor of  claim 4 , wherein said communications unit is further adapted for transferring data from internal registers of said processor and for transferring data to said internal registers of said processor.  
   
   
       6 . The processor of  claim 4 , wherein the second of said groups further comprises a second arithmetic logic unit combined with a memory access unit, said memory access unit being adapted for transferring data from an internal memory of said processor and for transferring data to said internal memory of said processor.  
   
   
       7 . The processor of  claim 4 , further comprising a third group of execution units.  
   
   
       8 . The processor of  claim 7 , wherein said third group of execution units comprises a branch unit adapted for performing branch operations.  
   
   
       9 . The processor of  claim 7 , wherein said third group of execution units comprises a multiplier unit.  
   
   
       10 . The processor of  claim 7 , wherein said third group of execution units comprises a multiplier accumulator unit.  
   
   
       11 . The processor of  claim 7 , wherein said third group of execution units comprises a unit for performing signal processing operations.  
   
   
       12 . The processor of  claim 1 , further comprising: 
 an instruction memory having a fixed width wherein: 
 said execution units are divided into a first group and at least a second group,  
 an instruction word, containing sub-instructions for an execution unit in the first group, has a first length,  
 an instruction word, containing sub-instructions for an execution unit in the second group, has a second length greater than said first length, and  
 the instruction memory is adapted to store instruction words of said first length and instruction words of said second length.  
   
   
   
       13 . A processor array, comprising: 
 an array of long instruction word processors; and    a plurality of communications buses interconnecting said long instruction word processors wherein each of said long instruction word processors further comprises: 
 a plurality of execution units, including at least an arithmetic logic unit and a communications unit adapted to transfer data from one of said communications buses or onto one of said communications buses; and  
 means for decoding instruction words containing sub-instructions, wherein: 
 said execution units are divided into a plurality of groups each containing at least one execution unit with the arithmetic logic unit and the communications unit being in different groups,  
 a single instruction word contains a sub-instruction for one of said execution units in each of said groups, and  
 a single instruction word contains a respective sub-instruction for a respective execution unit in at least one of said plurality of groups.