US2006156092A1PendingUtilityA1

Memory technology test apparatus

39
Individually held — no corporate assignee on recordPriority: Aug 29, 2002Filed: Jan 23, 2006Published: Jul 13, 2006
Est. expiryAug 29, 2022(expired)· nominal 20-yr term from priority
Inventors:Joseph M. Jeddeloh
G11C 2029/5004G11C 29/56
39
PatentIndex Score
0
Cited by
0
References
0
Claims

Abstract

A programmable control device that creates an environment for controlling, testing and evaluating memory designs. The control device provides automated testing of address eyes, data eyes and voltage margins. The control device interfaces with a conventional computer system, such as a personal computer (PC). The computer system gathers test data and outputs the data in a graphical format if desired. Since the control device is quickly re-programmable, new memory sequencing, control, timing and power techniques are rapidly proto-typed in an inexpensive and timely manner.

Claims

exact text as granted — not AI-modified
1 - 40 . (canceled)  
   
   
       41 . An automated method of testing a memory device comprising the steps of: 
 controlling the memory device such that the memory device performs one of a plurality of tests;    inputting test result data from the memory device;    evaluating characteristics of the memory device from the test result data; and    modifying the characteristics of the memory device and the manner in which the memory device is controlled based on the evaluation.    
   
   
       42 . The method of  claim 41  further comprising the step of outputting the test result data.  
   
   
       43 . The method of  claim 41  further comprising the step of printing the test result data.  
   
   
       44 . The method of  claim 41  further comprising the step of printing the test result data.  
   
   
       45 . The method of  claim 41  further comprising the step of storing the test result data.  
   
   
       46 . The method of  claim 41 , wherein said modifying step comprises modifying a timing of the memory device.  
   
   
       47 . The method of  claim 41 , wherein said modifying step comprises modifying a data eye associated with the memory device.  
   
   
       48 . The method of  claim 41  further comprising the steps of inputting address information from the memory device.  
   
   
       49 . The method of  claim 48 , wherein said modifying step comprises modifying an address eye associated with the memory device.  
   
   
       50 . The method of  claim 41  further comprising the step of inputting voltage information from the memory device.  
   
   
       51 . The method of  claim 50 , wherein said modifying step comprises adjusting a supply voltage of the memory device.  
   
   
       52 . The method of  claim 50 , wherein said modifying step comprises adjusting a reference voltage of the memory device.  
   
   
       53 . The method of  claim 41 , wherein said modifying step comprises modifying a manner in which data bit values are determined.  
   
   
       54 . The method of  claim 41  further comprising the step of configuring delay lines used to receive a clock signal.  
   
   
       55 . A method of testing a memory device comprising the steps of: 
 generating requests used to test the memory device;    testing the memory device based on the generated requests;    inputting test result data from the memory device;    evaluating characteristics of the memory device from the test result data; and    modifying at least one of the characteristics of the memory device or the manner in which the memory device is controlled based on the evaluation.    
   
   
       56 . The method of  claim 55  further comprising the step of outputting the test result data.  
   
   
       57 . The method of  claim 55  further comprising the step of printing the test result data.  
   
   
       58 . The method of  claim 55  further comprising the step of printing the test result data.  
   
   
       59 . The method of  claim 55  further comprising the step of storing the test result data.  
   
   
       60 . The method of  claim 55 , wherein said modifying step comprises modifying a timing of the memory device.  
   
   
       61 . The method of  claim 55 , wherein said modifying step comprises modifying a data eye associated with the memory device.  
   
   
       62 . The method of  claim 55  further comprising the steps of inputting address information from the memory device.  
   
   
       63 . The method of  claim 62 , wherein said modifying step comprises modifying an address eye associated with the memory device.  
   
   
       64 . The method of  claim 55  further comprising the step of inputting voltage information from the memory device.  
   
   
       65 . The method of  claim 64 , wherein said modifying step comprises adjusting a supply voltage of the memory device.  
   
   
       66 . The method of  claim 64 , wherein said modifying step comprises adjusting a reference voltage of the memory device.  
   
   
       67 . The method of  claim 55 , wherein said modifying step comprises modifying a manner in which data bit values are determined.  
   
   
       68 . The method of  claim 55  further comprising the step of configuring delay lines used to receive a clock signal.

Join the waitlist — get patent alerts

Track US2006156092A1 — get alerts on status changes and closely related new filings.

We store only your email — no account needed. See our privacy policy.