Transistor of volatile memory device with gate dielectric structure capable of trapping charges and method for fabricating the same

Abstract

The present invention relates to a transistor of a volatile memory device with gate dielectric structure capable of trapping charges and a method for fabricating the same. The transistor in a cell region of a volatile memory device includes a substrate of a first conductive type; a gate dielectric structure capable of trapping charges and formed on the substrate; a gate formed on the gate dielectric structure; a gate insulation layer formed on the gate; a source/drain of a second conductive type formed in a predetermined region of the substrate disposed beneath each lateral side of the gate; and a channel ion implantation region of the first conductive type formed in a predetermined region of the substrate disposed beneath the gate.

1 . A volatile memory device, comprising: 
 a transistor for use in a memory cell, the transistor including: 
 a substrate of a first conductive;  
 a gate dielectric structure capable of trapping charges and formed on the substrate;  
 a gate formed on the gate dielectric structure;  
 a gate insulation layer formed on the gate;  
 a source/drain of a second conductive type formed in a predetermined portion of the substrate disposed beneath each lateral side of the gate; and  
 a channel ion implantation region of the first conductive type formed in a predetermined region of the substrate disposed beneath the gate; and  
   a voltage generating means for controlling a threshold voltage of the transistor for use in the memory cell by implanting charges to the gate dielectric structure through supplying a predetermined voltage to each of the substrate, the gate and the source/drain.    
   
   
       2 . The volatile memory device of  claim 1 , wherein the gate dielectric structure includes: 
 a bottom gate dielectric layer formed on the substrate;    a middle gate dielectric layer for trapping charges formed on the bottom gate dielectric layer; and    a top gate dielectric layer formed on the middle gate dielectric layer.    
   
   
       3 . The volatile memory device of  claim 2 , wherein the voltage generating means increases a threshold voltage of the transistor for use in the memory cell by implanting electrons to the middle gate dielectric layer.  
   
   
       4 . The volatile memory device of  claim 2 , wherein the voltage generating means decreases a threshold voltage of the transistor for use in the memory cell by implanting holes to the middle gate dielectric layer.  
   
   
       5 . The volatile memory device of  claim 2 , wherein the bottom gate dielectric layer and the top gate dielectric layer are made of oxide and the middle gate dielectric layer is made of nitride.  
   
   
       6 . The volatile memory device of  claim 2 , wherein the bottom gate dielectric layer and the top gate dielectric layer are made of oxide and the middle gate dielectric layer is made of a material selected from a group consisting of oxynitride, aluminum oxide and hafnium oxide.