Non-volatile electrically alterable memory cell for storing multiple data and manufacturing thereof

Abstract

A memory cell that includes two control gates disposed laterally between two floating gates where each floating gate is capable of holding data. The memory cell is formed by placing a first polysilicon on a substrate of semiconductor material, on which a well is placed. The control gates are preferably formed by a Damascene process, in which a first polysilicon is removed after forming two floating gates, and a second polysilicon is placed between these two floating gates. An anisotropic etching is later done on the second polysilicon to form two control gates.

1 . A non-volatile memory device comprising: 
 a first trench isolation region;    a second trench isolation region apart from the first trench isolation region;    a control gate having a first width;    a first floating gate having a second width; and    a second floating gate having a third width, wherein the control gate being placed between the first and second floating gates and the first width of the control gate and the second and third widths of the first and second floating gates being defined by the first and second trench isolation regions.    
     
     
         2 . The non-volatile memory device of  claim 1 , wherein the first trench isolation region and the second trench isolation region are interconnected.  
     
     
         3 . A self-aligning method for defining the width of an active region of a non-volatile memory device using a mask, wherein the active region includes a control gate and two floating gates, comprising the steps of: 
 forming a first and a second field isolation regions using the mask; and    forming an active region of a non-volatile memory device between the first and second field isolation regions, the active region having a width defined by the first and second field isolation regions,    wherein the width of the active region further defines a width of the control gate and each of the two floating gates.    
     
     
         4 . The self-aligning method of  claim 3 , further comprising the step of connecting the first isolation region to the second isolation region.  
     
     
         5 . A self-aligned method for defining a channel length of a floating gate in a semiconductor structure, wherein the semiconductor structure includes a polysilicon layer, a plurality of blocks of a sacrificial material on the top of the polysilicon layer, and a layer of oxide material covering the semiconductor structure, comprising the steps of: 
 etching the oxide material to form a gate mask, the gate mask having a length; and    etching the sacrificial material and the polysilicon layer to form a floating gate under the gate mask, wherein the floating gate having a channel length defined by the length of the gate mask.    
     
     
         6 . A self-aligned method for manufacturing an electrically alterable memory device on a semiconductor layer having a top side, comprising the steps of: 
 growing an insulating layer on the top side of the semiconductor layer;    depositing a first conductive layer on the insulating layer, the first conductive layer having a top side;    forming a plurality of trench isolation regions along a first direction, a trench isolation region extending downwardly into the semiconductor layer;    depositing a layer of a sacrificial material on the top side of the first conductive layer, the layer of the sacrificial material having a top side;    etching the layer of the sacrificial material to form a plurality of isolation channels along a second direction, two adjacent isolation channels delimiting a block of the sacrificial material, the block of the sacrificial material having two lateral sides, a top, and a bottom;    forming two gate masks along two lateral sides of the block of the sacrificial material, one gate mask on each lateral side;    etching the first conductive layer to extend the plurality of isolation channels to the insulating layer, two adjacent isolation channels delimiting a block of the first conductive layer, the block of the first conductive layer being located under the block of the sacrificial material;    etching the block of the sacrificial material to form a control channel;    etching the block of the first conductive layer to form two lateral blocks of the first conductive layer under two gate masks, the two lateral blocks include a first lateral block and a second lateral block; and    filling the control channel with a second conductive layer.    
     
     
         7 . The method of  claim 6 , further comprising the step of extending the isolation channel to the semiconductor layer.  
     
     
         8 . The method of  claim 6 , further comprising the step of etching anisotropically the second conductive layer to form a first block and a second block of the second conductive layer, the first block of the second conductive layer facing the first block of the first conductive layer and the second block of the second conductive layer facing the second block of the first conductive layer.  
     
     
         9 . The method of  claim 8 , further comprising the step of forming a diffusion region on the semiconductor layer and between two blocks of the second conductive layer.  
     
     
         10 . The method of  claim 6 , further comprising the step of depositing an oxide layer to cover the entire memory device.  
     
     
         11 . The method of  claim 6 , wherein the second conductive layer having a width defined by two adjacent isolation channels.  
     
     
         12 . The method of  claim 6 , wherein the insulating layer is tunnel oxide.  
     
     
         13 . The method of  claim 6 , wherein the first conductive layer is a first polysilicon and the second conductive layer is a second polysilicon.  
     
     
         14 . The method of  claim 6 , wherein the sacrificial material is silicon nitride.  
     
     
         15 . The method of  claim 6 , wherein the step of forming a plurality of trench isolation regions along a first direction further comprises the steps of: 
 etching a trench channel extending from the top of the first conductive layer into a second semiconductor layer; and filling the trench channel with an oxide.    
     
     
         16 . The method of  claim 15 , wherein the step of filling the trench channel is done through a high density plasma oxide deposition.  
     
     
         17 . The method of  claim 15 , wherein the step of filling the trench channel is done through a chemical vapor deposition.  
     
     
         18 . The method of  claim 15 , wherein the step of filling the trench channel is done through a silicon glass deposition process.  
     
     
         19 . The method of  claim 15 , wherein the step of filling the trench channel is done through a spin-on-glass deposition process.  
     
     
         20 . The method of  claim 15 , further comprising the step of polishing the oxide in the trench channel through a chemical mechanical polishing process.  
     
     
         21 . The method of  claim 6 , wherein the step of forming a plurality of trench isolation regions along a first direction further comprises the steps of: 
 etching a trench channel extending from the top of the first conductive layer into the semiconductor layer; and    filling the trench channel with an oxide.    
     
     
         22 . The method of  claim 6 , further comprising the step of growing a liner oxide over the trench isolation regions.  
     
     
         23 . The method of  claim 6 , wherein the trench isolation region having a bottom, and further comprising the step of performing field implants on the bottom of the trench isolation region.  
     
     
         24 . The method of  claim 6 , further comprising the step of growing a layer of oxide spacer on the top of the isolation channels.  
     
     
         25 . The method of  claim 24 , further comprising the step of etching anisotropically the layer of oxide spacer.  
     
     
         26 . The method of  claim 6 , further comprising the step of forming a diffusion region at the bottom of an isolation channel by doping the bottom of the isolation channel with a first dopant.  
     
     
         27 . The method of  claim 26 , further comprising the step of growing a layer of liner oxide.  
     
     
         28 . The method of  claim 6 , further comprising the steps of: 
 etching the insulating layer to extend the control channel to a second semiconductors layer; and    performing a high voltage threshold implant on the bottom of the control channel.    
     
     
         29 . The method of  claim 6 , further comprising the step of growing a gate oxide on the bottom of the control channel.  
     
     
         30 . An electrically alterable memory device, comprising: 
 a first semiconductor layer doped with a first dopant in a first concentration;    a second semiconductor layer on top of the first semiconductor layer, doped with a second dopant that has an opposite electrical characteristic than the first dopant, the second semiconductor layer having a top side;    two spaced-apart diffusion regions embedded in the top side of the second semiconductor layer, each diffusion region doped with the first dopant in a second concentration greater than the first concentration, the two diffusion regions including a first diffusion region and a second diffusion region, and a first channel region defined between the first diffusion region and the second diffusion region;    a first floating gate having a first side, a second side, and a first height and comprised of a conductive material, the first floating gate disposed adjacent the first diffusion region and above the first channel region and separated therefrom by a first insulator region, the first floating gate capable of storing electrical charge;    a second floating gate having a first side, a second side, and a second height and comprised of a conductive material, the second floating gate disposed adjacent the second diffusion region and above the first channel region and separated therefrom by a second insulator region, the second floating gate capable of storing electrical charge;    a first control gate having a third height and comprised of a conductive material, the first control gate disposed laterally adjacent the first floating gate, the first control gate separated from the first side of the first floating gate by a first vertical insulator layer, the first control gate further being above the first channel region and separated therefrom by a third insulator region; and    a second control gate having a fourth height and comprised of a conductive material, the second control gate disposed laterally adjacent the second floating gate and the first control gate, the second control gate separated from the first side of the second floating gate by a second vertical insulator layer and separated from the first control gate by an oxide layer deposited between two control gates, the second control gate further being above the first channel region and separated therefrom by the third insulator region.    
     
     
         31 . The memory device of  claim 30 , further comprising a third diffusion region.  
     
     
         32 . The memory device of  claim 30 , wherein the first dopant having a P-type characteristic and the second dopant having an N-type characteristic.  
     
     
         33 . The memory device of  claim 30 , wherein the first dopant having an N-type characteristic and the second dopant having a P-type characteristic.  
     
     
         34 . The memory device of  claim 30 , wherein the first insulator region having a thickness that allows tunneling of charge between the first floating gate and the first channel region.  
     
     
         35 . The memory device of  claim 30 , wherein the third insulator region having a thickness that allows tunneling of charge between the second floating gate and the first channel region.  
     
     
         36 . The memory device of  claim 35 , wherein the thickness of the third insulator region is between 60 Angstroms and 110 Angstroms.  
     
     
         37 . The memory device of  claim 30 , wherein the first vertical insulator is made from an oxide-nitride-oxide having a thickness that provides capacitance between the first floating gate and the control gate, and the first vertical insulator preventing leakage between the first floating gate and the control gate.  
     
     
         38 . The memory device of  claim 30 , further comprising two shielding oxide layers, each shielding oxide layer placed adjacent to the second side of a floating gate.