Back-contacted solar cells with integral conductive vias and method of making

Abstract

Methods of manufacturing back-contacted p-type semiconductor substrate solar cells fabricated using a gradient-driven solute transport process, such as thermomigration or electromigration, to create n-type conductive vias connecting the n-type emitter layer on the front side to n-type ohmic contacts located on the back side, and back-contacted solar cells with integral n-type conductive vias, such as made by a gradient-driven solute transport process.

1 . A solar cell, comprising: 
 a substantially planar p-type bulk semiconductor substrate, having a front side and a back side;    a front side n +  diffusion emitter layer disposed on at least a portion of the front side of the semiconductor substrate;    at least one negative ohmic contact disposed on the back side of the semiconductor substrate; and    at least one n ++  doped conductive path with a substantially solid cross-section and including the semiconductor substrate material, wherein the conductive path is disposed within and through the semiconductor substrate and electrically connects the front side n +  emitter layer to the negative ohmic contact located on the back side of the semiconductor substrate.    
     
     
         2 . The solar cell of  claim 1  further comprising at least one positive ohmic contact located on the back side of the semiconductor substrate.  
     
     
         3 . The solar cell of  claim 1  wherein the at least one negative ohmic contact comprises a n-gridline negative ohmic contact.  
     
     
         4 . The solar cell of  claim 2  wherein the at least one positive ohmic contact comprises a p-gridline positive ohmic contact.  
     
     
         5 . The solar cell of  claim 1  wherein the front side n +  diffusion emitter layer comprises a phosphorus n +  diffusion layer.  
     
     
         6 . The solar cell of  claim 1  further comprising a n +  diffusion emitter layer disposed over at least a portion of the back side of the semiconductor substrate.  
     
     
         7 . The solar cell of  claim 6  wherein the front side n +  diffusion emitter layer is lightly doped, and the back side n +  diffusion emitter layer is heavily doped.  
     
     
         8 . The solar cell of  claim 6 , further comprising a passivation layer disposed on the back surface of the semiconductor substrate, and disposed in-between the positive and negative ohmic contacts.  
     
     
         9 . The solar cell of  claim 1  further comprising an anti-reflection coating disposed on the front surface of the semiconductor substrate, covering the front side n +  diffusion emitter layer and conductive via.  
     
     
         10 . The solar cell of  claim 1  wherein the n ++  doped conductive path comprises one or more n-type dopant materials selected from the group consisting of phosphorus, arsenic, and antimony.  
     
     
         11 . The solar cell of  claim 1  further comprising an array of closely-spaced n ++  doped conductive passages.  
     
     
         12 . The solar cell of  claim 11  wherein the n ++  doped conductive passages are approximately circular in cross section.  
     
     
         13 . The solar cell of  claim 12  wherein the diameter of the approximately circular cross section of the conductive passages is from about 25 microns to about 150 microns.  
     
     
         14 . The solar cell of  claim 11  wherein the n ++  doped conductive passages are approximately rectangular in cross section, with a short axis and a long axis.  
     
     
         15 . The solar cell of  claim 14  wherein the length of the short axis of the approximately rectangular conductive passages is from about 25 microns to about 150 microns.  
     
     
         16 . The solar cell of  claim 14  wherein the length of the long axis of the approximately rectangular conductive passages is substantially longer than the short axis.  
     
     
         17 . The solar cell of  claim 14  wherein the long axis of each of the approximately rectangular conductive passages extends across more than one-half of a dimension of the substantially planar p-type bulk semiconductor substrate.  
     
     
         18 . The solar cell of  claim 11  wherein the spacing between adjacent conductive vias is from about 1 mm to about 2 mm.  
     
     
         19 . The solar cell of  claim 1  wherein the at least one n ++  doped conductive path is made by a gradient-driven migration process.  
     
     
         20 . The solar cell of  claim 19 , wherein the gradient-driven migration process comprises a thermomigration process, an electromigration process, or a combination of both.  
     
     
         21 . The solar cell of  claim 1  wherein the substantially planar p-type bulk semiconductor substrate does not have connecting holes between the front side and the back side.  
     
     
         22 . A process for fabricating a back-contacted semiconductor solar cell, comprising: 
 providing a p-type semiconductor substrate with a front surface and a back surface;    forming an n +  emitter layer over at least a portion of the front surface and back surface of the p-type semiconductor substrate;    depositing n-type dopant solute material on a portion of one surface of the p-type semiconductor substrate;    migrating the n-type dopant solute material through the p-type semiconductor substrate, whereby one or more substantially solid n ++  doped conductive vias are formed that electrically connect the front surface n +  emitter layer to the back surface n +  emitter layer; and    providing one or more negative contact back surface ohmic contacts, wherein each negative contact back surface ohmic contact is electrically connected with at least one substantially solid n ++  doped conductive via.    
     
     
         23 . The process of  claim 22  wherein forming an n +  emitter layer comprises diffusing phosphorus.  
     
     
         24 . The process of  claim 23  wherein forming an n +  emitter layer comprises the steps of: 
 providing a patterned diffusion barrier covering an area where a p-type ohmic contact will be formed;    diffusing phosphorus into the front and back surfaces of the semiconductor substrate to form front side and back side n +  emitter layers; and    removing the patterned diffusion barrier.    
     
     
         25 . The process of  claim 24  wherein providing a patterned diffusion barrier comprises screen-printing a patterned diffusion barrier.  
     
     
         26 . The process of  claim 24  wherein providing a patterned diffusion barrier comprises a thermally grown, nitride deposited, laser patterned or ink jet printed diffusion barrier.  
     
     
         27 . The process of  claim 22  wherein the n-type dopant solute material comprises a closely-spaced array of droplets or lines of solute material.  
     
     
         28 . The process of  claim 22  wherein migrating the n-type dopant solute material comprises thermomigrating or electromigrating the solute material in a thermal processor.  
     
     
         29 . The process of  claim 28 , wherein the thermal processor comprises a bank of plasma arc lamps to heat one side of the semiconductor substrate.  
     
     
         30 . The process of  claim 22  further comprising, prior to depositing the array, forming one or more shallow indentations on the front surface of the semiconductor substrate in the location where the n-type dopant solute material is to be deposited.  
     
     
         31 . The process of  claim 30  wherein the one or more shallow indentations comprise pits or grooves and the n-type dopant solute material comprises droplets of solute material.  
     
     
         32 . The process of  claim 22  wherein providing one or more negative contact back surface ohmic contacts comprises screen-printing silver paste for an array of negative-polarity n-type ohmic contacts.  
     
     
         33 . The process of  claim 22  further comprising providing an array of positive contact back surface ohmic contacts.  
     
     
         34 . The process of  claim 33  wherein providing an array of positive back contact surface ohmic contacts comprises screen-printing silver paste for positive-polarity p-type ohmic contacts.  
     
     
         35 . The process of  claim 33  wherein providing an array of positive back contact surface ohmic contacts comprises forming positive contacts by alloying aluminum through the back surface n +  emitter layer.  
     
     
         36 . The process of  claim 22  further comprising, after migrating the n-type dopant solute material, depositing an anti-reflection coating on the front surface-of the semiconductor substrate, covering the front side n +  emitter layer and the conductive vias.  
     
     
         37 . The process of  claim 22  further comprising, prior to providing one or more negative contact back surface ohmic contacts, depositing a dielectric passivation layer on the back side of the semiconductor substrate.  
     
     
         38 . The process of  claim 37  wherein the passivation layer is patterned to not cover the areas where ohmic contacts are to be applied.