System, method and storage medium for providing programmable delay chains for a memory system

Abstract

A memory system including a plurality of delay lines and a processor in communication with the delay lines. The delay lines are in communication with a bus attached to a memory device. The bus includes a plurality of wires and each of the delay lines corresponds to on of the plurality of wires. The processor receives a plurality of data bits and a data strobe via the wires on the bus. Each of the data bits includes data eye. The process also automatically calibrates the target data eye of each of the data bits and corresponds to the target data eye. In addition, the processor centers the data strobe over the target data eye.

1 . A memory system comprising: 
 a plurality of delay lines in communication with a bus attached to a memory device, wherein the bus includes a plurality of wires and each of the delay lines corresponds to one of the plurality of wires; and    a processor in communication with the delay lines for: 
 receiving a plurality of data bits and a data strobe via the wires on the bus, wherein each of the data bits includes a data eye;  
 automatically calibrating a target data eye for the data bits;  
 adjusting the delay lines so that the data eye of each of the data bits corresponds to the target data eye; and  
 centering the data strobe over the target data eye.  
   
   
   
       2 . The system of  claim 1  wherein the automatically calibrating includes selecting a latest arriving bit from the plurality of bits and using the data eye of the latest arriving data bit as the target data eye.  
   
   
       3 . The system of  claim 1  wherein the plurality of data bits are read data bits and the data strobe is a read data strobe.  
   
   
       4 . The system of  claim 1  wherein the plurality of data bits are write data bits and the data strobe is a write data strobe.  
   
   
       5 . The system of  claim 1  wherein the instructions are implemented by circuitry.  
   
   
       6 . The system of  claim 1  wherein the instructions are implemented by software.  
   
   
       7 . The system of  claim 1  wherein the instructions are implemented by a combination of circuitry and software.  
   
   
       8 . The system of  claim 1  wherein the delay lines are multiplexor chains.  
   
   
       9 . A method for providing programmable delay chains in a memory system, the method comprising: 
 receiving a plurality of data bits and a data strobe via wires on a bus, wherein each of the data bits includes a data eye, and the memory system includes a plurality of delay lines in communication with the wires on the bus; and    automatically calibrating a target data eye for the data bits;    adjusting the delay lines so that the data eye of each of the data bits corresponds to the target data eye; and    centering the data strobe over the target data eye.    
   
   
       10 . The method of  claim 9  wherein the automatically calibrating includes selecting a latest arriving bit from the plurality of bits and using the data eye of the latest arriving data bit as the target data eye.  
   
   
       11 . The method of  claim 9  wherein the plurality of data bits are read data bits and the data strobe is a read data strobe.  
   
   
       12 . The method of  claim 9  wherein the plurality of data bits are write data bits and the data strobe is a write data strobe.  
   
   
       13 . The method of  claim 9  wherein the instructions are implemented by circuitry.  
   
   
       14 . The method of  claim 9  wherein the instructions are implemented by software.  
   
   
       15 . The method of  claim 9  wherein the instructions are implemented by a combination of circuitry and software.  
   
   
       16 . The method of  claim 9  wherein the delay lines are multiplexor chains.  
   
   
       17 . A storage medium encoded with machine readable computer program code for providing programmable delay chains in a memory system, the storage medium including instructions for causing a computer to implement a method comprising: 
 receiving a plurality of data bits and a data strobe via wires on a bus, wherein each of the data bits includes a data eye, the memory system includes a plurality of delay lines in communication with the wires on the bus; and    automatically calibrating a target data eye for the data bits;    adjusting the delay lines so that the data eye of each of the data bits corresponds to the target data eye; and    centering the data strobe over the target data eye.