Vertical replacement-gate junction field-effect transistor

Abstract

An architecture for creating a vertical JFET. Generally, an integrated circuit structure includes a semiconductor area with a major surface formed along a plane and a first source/drain doped region formed in the surface. A second doped region forming a channel of different conductivity type than the first region is positioned over the first region. A third doped region is formed over the second doped region having an opposite conductivity type with respect to the second doped region, and forming a source/drain region. A gate is formed over the channel to form a vertical JFET. In an associated method of manufacturing the semiconductor device, a first source/drain region is formed in a semiconductor layer. A field-effect transistor gate region, including a channel and a gate electrode, is formed over the first source/drain region. A second source/drain region is then formed over the channel having the appropriate conductivity type.

1 . A process for fabricating an integrated circuit structure comprising: 
 providing a semiconductor substrate;    forming in the semiconductor substrate a first device region of a first conductivity type, the first device region selected from the group consisting of a source region and a drain region;    forming a multilayer stack comprising at least three material layers over the first device region;    forming a first and a second window in the multilayer stack, wherein the first and second windows terminate at the first device region;    forming a semiconductor material within the first and the second windows to form a first and a second semiconductor plug each having a first end and a second end, wherein the first end of each semiconductor plug is in contact with the first device region, and wherein the first and the second semiconductor plugs are of a second conductivity type;    forming a second device region of the first conductivity type at the second end of the first semiconductor plug, the second device region selected from the group consisting of a source region and a drain region, wherein one of the first and the second device regions is a source region and the other is a drain region;    forming a third device region of the first conductivity type at the second end of the second semiconductor plug, the third device region selected from the group consisting of a source region and a drain region, wherein one of the first and the third device regions is a source region and the other is a drain region;    removing a material layer of the multilayer stack to expose a portion of the first and the second semiconductor plugs;    forming a dielectric material layer on the exposed portion of the first semiconductor plug;    forming a region of the first conductivity type on the exposed portion of the second semiconductor plug; and    forming a gate electrode in contact with the dielectric material layer.    
   
   
       2 . The process of  claim 1  wherein the material layer of the multilayer stack is removed by etching, wherein a first layer of the multilayer stack has a first etch rate, the second material layer has a second etch rate, and a third material layer has a third etch rate, and wherein the second etch rate is at least ten times faster than the first etch rate.  
   
   
       3 . The process of  claim 2  wherein a material of the first material layer and the third material layer comprises an electrically insulating material.  
   
   
       4 . The process of  claim 2  further comprising the step of forming an etch stop layer over the first material layer, over the second material layer or over both of the first and second material layers.  
   
   
       5 . The process of  claim 1  further comprising forming a diffusion barrier layer over the first device region before forming the multilayer stack.  
   
   
       6 . A process for fabricating a vertical transistor comprising: 
 providing a semiconductor substrate;    forming in the semiconductor substrate a first device region of a first conductivity type, the first device region selected from the group consisting of a source region and a drain region;    forming a multilayer stack comprising at least three material layers over the first device region;    forming a window in the multilayer stack extending to the first device region;    forming semiconductor material within the window to form a semiconductor plug in the multilayer stack, wherein the semiconductor plug comprises a first end in contact with the first device region and a second end, and wherein a material of the semiconductor plug is of a second conductivity type;    forming a second device region of the first conductivity type at the second end of the semiconductor plug, the second device region selected from the group consisting of a source region and a drain region, wherein one of the first and second device regions is a source region and the other is a drain region;    removing a material layer of the multilayer stack to expose a portion of the semiconductor plug; and    forming a region of the first conductivity type on the exposed portion of the semiconductor plug.    
   
   
       7 . The process of  claim 6  wherein the multilayer stack comprises a first, a second and a third material layer, and wherein the step of removing the material layer comprises etching the second material layer, and wherein the first layer has a first etch rate, the second layer has a second etch rate, and the third layer has a third etch rate, and wherein the second etch rate is at least ten times faster than the first etch rate.  
   
   
       8 . The process of  claim 7  wherein a material of the first material layer and the third material layer comprises an electrically insulating material.  
   
   
       9 . The process of  claim 7  further comprising a step of forming an etch stop layer over the first material layer, over the second material layer or over both the first and the second material layers.  
   
   
       10 . The process of  claim 6  further comprising forming a diffusion barrier layer over the first device region before forming the multilayer stack.  
   
   
       11 . An integrated circuit structure comprising first and second vertical field-effect transistors, wherein the first vertical field-effect transistor comprises: 
 a semiconductor substrate having a major surface formed along a plane;    a first doped region of a first conductivity type formed in the surface;    a second doped region of a second conductivity type overlying the first doped region;    a third doped region of the first conductivity type overlying the second doped region;    a dielectric material layer adjacent the second doped region;    a first gate adjacent the dielectric material layer;    wherein the second vertical field-effect transistor comprises:    a fourth doped region of the first conductivity type formed in the surface;    a fifth doped region of the second conductivity type overlying the fourth doped region;    a sixth doped region of the first conductivity type overlying the fifth doped region; and    a second gate of the first conductivity type adjacent the fifth doped region.    
   
   
       12 . The integrated circuit structure of  claim 11  further comprising a diffusion barrier layer overlying the first doped region.  
   
   
       13 . The integrated circuit structure of  claim 11  wherein the second and the third doped regions are formed within a respective first and a second window formed in material layers overlying the semiconductor substrate.  
   
   
       14 . The integrated circuit structure of  claim 11  wherein the first and the second gates comprise a material selected from the group consisting of doped polysilicon crystalline, doped amorphous silicon, doped silicon-germanium, doped silicon-germanium-carbon, metals and metal compounds.  
   
   
       15 . The integrated circuit structure of  claim 14  wherein the metals and metal compounds are selected from the group consisting of titanium, titanium nitride, tungsten, tungsten suicide, tantalum, tantalum nitride, molybdenum, aluminum and copper.  
   
   
       16 . The integrated circuit structure of  claim 11  wherein the first and the fourth doped regions comprise a first source/drain region of a respective first and second field effect transistor, the second and the fifth doped regions comprise a channel region of the respective first and second field effect transistors, and the third and the sixth doped region comprise a second source/drain region of the respective first and second field effect transistors.  
   
   
       17 . A field-effect transistor structure comprising: 
 a semiconductor substrate having a major surface along a plane;    a first doped region of a first conductivity type disposed in the surface;    a second doped region of a second conductivity type overlying the first doped region;    a third doped region of the first conductivity type overlying the second doped region; and    a gate region of the first conductivity type adjacent the second doped region.    
   
   
       18 . A field effect transistor structure comprising: 
 a semiconductor substrate having a major surface formed along a plane;    a first doped region of a first conductivity type disposed in the surface;    a first insulating layer overlying the first doped region;    a first etch stop layer overlying the first insulating layer;    a second insulating layer overlying the first etch stop layer;    a second etch stop layer overlying the second insulating layer;    a third insulating layer overlying the second etch stop layer;    a second doped region of a second conductivity type disposed in a window extending downwardly from the third insulating region through the first insulating region;    a third doped region of the first conductivity type overlying the second doped region;    a fourth doped region of the second conductivity type disposed on an exposed surface of the second doped region.