Through-substrate interconnect structures and assemblies

Abstract

Through-substrate interconnect structures and assemblies are disclosed. A substrate includes at least one via passing therethrough. The via may have an enlarged central portion, and one or more end portions which taper to smaller end surfaces. The one or more via end portions may be trapezoidal in shape. The one or more via end portions may have a rounded, i.e., frustoconical, shape. The shape is conducive to improved solder ball/bump attachment, and enables forming vias of very small diameter and pitch.

1 . A through-wafer interconnect comprising a conductive via member passing through a wafer between a first surface and a second, opposing surface, the via member having a first exposed end and a second exposed end, the first end comprising one of a trapezoid shape and a frustoconical shape and the second end comprising one of a shape flaring out as it becomes more distal from the second surface and a post shape having a substantially constant lateral extent.  
   
   
       2 . A through-wafer interconnect comprising a conductive via member passing through a wafer between a first surface and a second, opposing surface, the wafer being thinned from an initial thickness to expose a first end of the via member as one of a trapezoid shape and a frusto-conical shape, and the second surface of the wafer exposing only an end surface of a second end of the via member comprising one of a shape flaring out as it approaches the second surface and a post shape having a substantially constant lateral extent.  
   
   
       3 . A through-wafer interconnect comprising a conductive via member passing through a wafer having a first surface and a second, opposing surface, the conductive via member having a first exposed end and a second exposed end, the first exposed end and the second exposed end each comprising one of a trapezoid shape and a frustoconical shape.  
   
   
       4 . A via-containing member, comprising: 
 a substrate having a first surface and a second, opposing surface;    a pattern of vias in the substrate, each via passing through the substrate and having a first end and a second, opposing end, wherein the vias comprise: 
 a first end having at least one of a trapezoidal shape and a frustoconical shape and extending outwardly from one of the first surface and the second, opposing surface; and  
 a second via end having at least one of a flared-out shape and a post shape having a substantially constant lateral extent.  
   
   
   
       5 . The via-containing member in accordance with  claim 4 , wherein the second via end having at least one of the flared-out shape and post shape extends outwardly from another of the first surface and the second, opposing surface.  
   
   
       6 . A via-containing member comprising: 
 a substrate having first and second opposing surfaces; and    a pattern of vias on the substrate, each via passing through the substrate between a first end and an opposing second end, the first end and the second, opposing end each having one of a trapezoidal shape and a frustoconical shape.    
   
   
       7 . The via-containing member in accordance with  claim 6 , wherein the via-containing member comprises one of a wafer contact test card, a single die interposer, and a multi-die interconnect.  
   
   
       8 . A semiconductor device assembly, comprising: 
 at least one semiconductor die having a plurality of bond pads on an active surface thereof; and    an interposer comprising a substrate having a plurality of conductive vias extending therethrough in alignment with bond pads of the plurality, the plurality of conductive vias each including a via end having a substantially flat end surface projecting from a substrate surface facing the at least one semiconductor die and in contact with a bond pad of the plurality, the via end tapering from a larger lateral extent proximate the substrate surface to a smaller lateral extent distal therefrom.    
   
   
       9 . The semiconductor device assembly of  claim 8 , further including a dielectric material interposed between the active surface of the at least one semiconductor die and the surface of the substrate and surrounding the projecting via ends.  
   
   
       10 . The semiconductor device assembly of  claim 8 , further including a metal overlay over at least the substantially flat end surface.  
   
   
       11 . The semiconductor device assembly of  claim 8 , wherein ends of the plurality of vias opposite the projecting via ends lie substantially coplanar with another surface of the substrate, and further including: 
 conductive traces extending laterally across the another surface from the substantially coplanar via ends; and    discrete conductive elements disposed on distal ends of the conductive traces and projecting outwardly from the another surface.    
   
   
       12 . The semiconductor device assembly of  claim 11 , further comprising a dielectric layer over the another surface and laterally surrounding the discrete conductive elements.  
   
   
       13 . The semiconductor device assembly of  claim 8 , wherein the projecting via ends are in direct contact with the plurality of bond pads.  
   
   
       14 . The semiconductor device assembly of  claim 8 , wherein the projecting via ends are in contact with the plurality of bond pads through intervening discrete conductive elements.  
   
   
       15 . A semiconductor device assembly, comprising: 
 at least one semiconductor die having a plurality of bond pads on an active surface thereof; and    an interposer comprising a substrate having a plurality of conductive vias extending therethrough in alignment with bond pads of the plurality, the plurality of conductive vias each including a first via end having a substantially flat end surface projecting from a substrate surface opposite a substrate surface facing the at least one semiconductor die and tapering from a larger lateral extent proximate the substrate to a smaller lateral extent distal therefrom and a second via end substantially coplanar with the substrate surface facing the at least one semiconductor die and in contact with a bond pad of the plurality through a discrete conductive element projecting from the substrate.    
   
   
       16 . The semiconductor device assembly of  claim 15 , further including a dielectric material interposed between the active surface of the at least one semiconductor die and the substrate and surrounding the discrete conductive elements.  
   
   
       17 . The semiconductor device assembly of  claim 15 , further including: 
 conductive traces extending laterally across the surface of the substrate facing the at least one semiconductor die from the substantially coplanar via ends; and    wherein the discrete conductive elements lie at distal ends of the conductive traces.    
   
   
       18 . A semiconductor device assembly, comprising: 
 at least one semiconductor die having a plurality of bond pads on an active surface thereof; and    at least another semiconductor die having a plurality of conductive vias extending therethrough in alignment with bond pads of the plurality of the at least one semiconductor die, the plurality of conductive vias each including a via end having a substantially flat end surface projecting from a surface of the at least another semiconductor die facing the at least one semiconductor die and in contact with a bond pad of the plurality, the via end tapering from a larger lateral extent proximate the surface of the at least another semiconductor die facing the at least one semiconductor die to a smaller lateral extent distal therefrom.    
   
   
       19 . The semiconductor device assembly of  claim 18 , further including a dielectric material interposed between the active surface of the at least one semiconductor die and the at least another semiconductor die and surrounding the projecting via ends.  
   
   
       20 . The semiconductor device assembly of  claim 18 , further including a metal overlay over at least the substantially flat end surface.  
   
   
       21 . The semiconductor device assembly of  claim 18 , wherein ends of the plurality of vias opposite the projecting via ends lie substantially coplanar with another surface of the at least another semiconductor die, and further including: 
 conductive traces extending laterally across the another surface from the substantially coplanar via ends; and    discrete conductive elements disposed on distal ends of the conductive traces and projecting outwardly from the another surface.    
   
   
       22 . The semiconductor device assembly of  claim 21 , further comprising a dielectric layer over the another surface and laterally surrounding the discrete conductive elements.  
   
   
       23 . The semiconductor device assembly of  claim 18 , wherein the projecting via ends are in direct contact with the plurality of bond pads.  
   
   
       24 . The semiconductor device assembly of  claim 8 , wherein the projecting via ends are in contact with the plurality of bond pads through intervening discrete conductive elements.  
   
   
       25 . A semiconductor device assembly, comprising: 
 at least one semiconductor die having a plurality of bond pads on an active surface thereof, and    an interposer comprising a substrate having a plurality of conductive vias extending therethrough in alignment with bond pads of the plurality, the plurality of conductive vias each including a first via end having a substantially flat end surface projecting from a substrate surface facing the at least one semiconductor die and in contact with a bond pad of the plurality and a second via end projecting from a substrate surface facing away from the at least one semiconductor die, the first and second via ends tapering from a larger lateral extent proximate the substrate to a smaller lateral extent distal therefrom.    
   
   
       26 . The semiconductor device assembly of  claim 25 , further including a dielectric material interposed between the active surface of the at least one semiconductor die and the surface of the substrate and surrounding the projecting first via ends.  
   
   
       27 . The semiconductor device assembly of  claim 25 , further including a metal overlay over at least the substantially flat end surface.  
   
   
       28 . The semiconductor device assembly of  claim 25 , wherein the second ends of the plurality of vias include discrete conductive elements disposed thereon.  
   
   
       29 . The semiconductor device assembly of  claim 25 , wherein the at least one semiconductor die comprises a plurality of semiconductor dice mutually laterally adjacently disposed in substantially coplanar fashion over the substrate.  
   
   
       30 . The semiconductor device assembly of  claim 28 , further comprising a dielectric layer over the another surface and laterally surrounding the discrete conductive elements.  
   
   
       31 . The semiconductor device assembly of  claim 25 , wherein the projecting first via ends are in direct contact with the plurality of bond pads.  
   
   
       32 . The semiconductor device assembly of  claim 25 , wherein the projecting first via ends are in contact with the plurality of bond pads through intervening discrete conductive elements.  
   
   
       33 . The semiconductor device assembly of  claim 25 , wherein the substrate includes a recess therein facing the at least one semiconductor die and the at least one semiconductor die is aligned with the recess, and further including at least another semiconductor die having a plurality of bond pads on an active surface thereof superimposed over the at least one semiconductor die and in communication with the first via ends of vias of the plurality laterally adjacent the at least one semiconductor die and projecting at least beyond the active surface thereof.  
   
   
       34 . The semiconductor device assembly of  claim 33 , wherein the substrate exhibits an increased thickness in a region surrounding the recess, and the vias of the plurality laterally adjacent the at least one semiconductor die extend through the region.