Systems and methods for implementing logic in a processor

Abstract

Systems, methods and media for implementing logic in the arithmetic/logic unit of a processor are disclosed. More particularly, hardware is disclosed for computing logical operations with minimal hardware by organizing the execution unit such that the propagate and generate functions required for the adder can be used as a basis to implement the bitwise logical instructions. The result of these functions is computed before execution of the instruction by an execution macro in the arithmetic/logic unit.

1 . A method for implementing logic in an arithmetic/logic unit, comprising: 
 receiving two operands;    computing a generate function result that is a logical AND or a logical NAND of the two operands;    computing a propagate function result that is a logical OR or a logical NOR of the two operands;    transmitting the generate function result to an execution macro of the arithmetic/logic unit that can compute the complement of the generate function result;    transmitting the propagate function result to an execution macro of the arithmetic/logic unit that can compute the complement of the propagate function result;    transmitting the generate function result and the propagate function result to an execution macro of the arithmetic/logic unit that can compute a logical complement and a logical NAND or a logical AND to produce a logical XOR of the two operands and a logical EQV of the two operands.    
     
     
         2 . The method of  claim 1 , further comprising selecting between a value and a logical complement of the value to determine which operand is received.  
     
     
         3 . The method of  claim 1 , further comprising computing a sum of the two operands.  
     
     
         4 . The method of  claim 1 , further comprising receiving a result of a function performed by an execution macro as an input for an next instruction to be executed.  
     
     
         5 . The method of  claim 1 , further comprising rotating an operand.  
     
     
         6 . The method of  claim 4 , wherein a first operand is replaced by logical one in response to a command to the arithmetic/logic unit to rotate a second operand.  
     
     
         7 . The method of  claim 1 , wherein a value produced by the generate function is passed to the rotator with a command to rotate by zero.  
     
     
         8 . An arithmetic/logic unit, comprising 
 a generate function preceding an execution macro, that generates a logical AND or a logical NAND of two operands;    a propagate function preceding an execution macro, that generates a logical OR or a logical NOR of the two operands;    complementation circuitry within an execution macro that receives a generate function result, to compute the complement of the generate function;    complementation circuitry within an execution macro that receives a propagate function result, to compute the complement of the propagate function; and    an execution macro, comprising an inverter and a NAND or AND gate, that receives a generate function result and a propagate function result and computes operations comprising a logical XOR of the two operands and a logical EQV of the two operands.    
     
     
         9 . The arithmetic/logic unit of  claim 8 , further comprising a selector that selects between a value and a logical complement of the value to determine one of the two operands.  
     
     
         10 . The arithmetic/logic unit of  claim 8 , wherein an execution macro comprises an adder.  
     
     
         11 . The arithmetic/logic unit of  claim 8 , wherein an execution macro comprises a rotator.  
     
     
         12 . The arithmetic/logic unit of  claim 11 , wherein a first operand is replaced by logical one in response to a command to the arithmetic/logic unit to rotate a second operand.  
     
     
         13 . The arithmetic/logic unit of  claim 11 , further comprising circuitry to accept a command to rotate the generate function result by zero.  
     
     
         14 . A computer system for processing instructions and data, comprising 
 a memory for storing the instructions and data;    a generate function, external to an adder, that generates a logical AND or a logical NAND of two operands of the data received from the memory;    a propagate function, external to an adder, that generates a logical OR or a logical NOR of the two operands;    an adder that receives a result from the generate function and a result from the propagate function and computes the sum of the two operands;    an execution macro, comprising an inverter and a NAND or AND gate, that receives a generate function result and a propagate function result and computes operations comprising a logical XOR of the two operands and a logical EQV of the two operands.    
     
     
         15 . The system of  claim 14 , further comprising complementation circuitry that computes the complement of the generate function.  
     
     
         16 . The system of  claim 14 , further comprising complementation circuitry that computes the complement of the propagate function;.  
     
     
         17 . The system of  claim 14 , further comprising a rotator.  
     
     
         18 . The system of  claim 16 , further comprising a control circuit to replace an operand by a logical 1 in response to a rotate command.  
     
     
         19 . The system of  claim 16 , further comprising circuitry to accept a command to rotate the generate function result by zero.  
     
     
         20 . The system of  claim 14 , further comprising a selector that selects a value or a complement of the value to determine one of the two operands.