Memory interface and method of interfacing between functional entities

Abstract

A data and signal interface for controlling the transfer of data and signals between a memory array and macro function such as that of a digital signal processor (DSP) core. In one embodiment, the interface comprises a plurality of memory ports which interface with X/Y memory banks, a plurality of function ports, each with a function controller, which interface with DSP functions, a crossbar connecting the memory and function ports, and an arbitration unit for arbitrating memory access by the function ports. The memory interface advantageously allows multiple simultaneous accesses of memory banks via a plurality of macro functions, each access under the control of a parent processor instruction. A standardized protocol used for memory read/write operations is also disclosed.

1 .- 30 . (canceled)  
     
     
         31 . A method of designing a user-configured and extended processor apparatus having a processor interface device, secondary processing function, and memory associated therewith, the method comprising: 
 providing a user-configurable and extendable primary processor core having an instruction set;    extending said primary core with at least one secondary processor function extension;    configuring said apparatus with at least one input/output (I/O) related function;    wherein said secondary processing function and I/O extensions comprise a portion of said instruction set; and    wherein said secondary processing function and I/O extensions have direct memory access (DMA) to said primary processor core.    
     
     
         32 . The method of  claim 31 , wherein said designing further comprises generating a description language model by: 
 receiving one or more inputs from a user for at least one customizable parameter of the primary processor core;    providing at least one prototype description of the primary processor core for which a model is being generated; and    generating through an automated process a description language model based on the least one customizable parameter and the at least one prototype description, said act of generating comprising modifying or substituting at least portions of said at least one prototype description.    
     
     
         33 . The method of  claim 32 , further comprising generating test code associated with said customized description language using an automated process and based at least in part on the at least one customizable parameter.  
     
     
         34 . The method of  claim 32 , wherein the description language model includes both functional and structural description language descriptions for at least the primary processor core.  
     
     
         35 . The method of  claim 32 , wherein said instruction set comprises both base and extension instructions.  
     
     
         36 . The method of  claim 31 , wherein said secondary processing function comprises a digital signal processing (DSP) function.  
     
     
         37 . The method of  claim 31 , further comprising extending said primary processor core with at least one 3G-related extension selected from the group consisting of: (i) turbo coding or decoding, and (ii) convolutional coding or decoding.  
     
     
         38 . A user-configured and extended processor apparatus having a processor interface device, secondary processing function, and memory associated therewith, the processor apparatus being designed according to the method comprising: 
 providing a user-configurable and extendable primary processor core having an instruction set;    extending said primary core with at least one secondary processor function extension;    configuring said apparatus with at least one input/output (I/O) related function;    wherein said secondary processing function and I/O extensions comprise a portion of said instruction set; and    wherein said secondary processing function and I/O extensions have direct memory access (DMA) to said primary processor core.    
     
     
         39 . The processor apparatus of  claim 38 , wherein said designing further comprises generating a description language model by: 
 receiving one or more inputs from a user for at least one customizable parameter of the primary processor core;    providing at least one prototype description of the primary processor core for which a model is being generated; and    generating through an automated process a description language model based on the least one customizable parameter and the at least one prototype description, said act of generating comprising modifying or substituting at least portions of said at least one prototype description.    
     
     
         40 . The processor apparatus of  claim 39 , further comprising generating test code associated with said customized description language using an automated process and based at least in part on the at least one customizable parameter.  
     
     
         41 . The processor apparatus of  claim 39 , wherein the description language model includes both functional and structural description language descriptions for at least the primary processor core.  
     
     
         42 . The processor apparatus of  claim 39 , wherein said instruction set comprises both base and extension instructions.  
     
     
         43 . The processor apparatus of  claim 38 , wherein said secondary processing function comprises a digital signal processing (DSP) function.  
     
     
         44 . The method of  claim 38 , further comprising extending said primary processor core with at least one 3G-related extension selected from the group consisting of: (i) turbo coding or decoding, and (ii) convolutional coding or decoding.  
     
     
         45 . A method of designing a user-configurable and extendable processing apparatus, the method comprising: 
 providing a software representation of a user-configurable and extendable processor core having an instruction set;    providing a software representation of a memory array;    providing a software representation of at least one macro function optimized for specific processing tasks;    providing software representation of at least one interface between said array and said at least one macro function; and    generating a design of said processing apparatus based at least in part on said software descriptions of said processor core, at least one macro function, memory array and at least one interface;    wherein said at least one macro function comprises an extension of said processor core.    
     
     
         46 . The method of  claim 45 , wherein said at least one macro function is substantially under control of said processor core via one or more customized instructions within a base or extension instruction sets of said processor core.  
     
     
         47 . The method of  claim 46 , wherein said one or more customized instructions act on data transferred to or out of said memory array in a pipelined fashion via said interface.  
     
     
         48 . The method of  claim 45 , wherein said method of designing further comprises generating a description language model by at least: 
 receiving one or more inputs from a user for at least one customizable parameter of the processor core;    providing at least one prototype description of the processor core for which a model is being generated; and    generating through an automated process a description language model based on the least one customizable parameter and the at least one prototype description, said act of generating comprising modifying or substituting at least portions of said at least one prototype description.    
     
     
         49 . The method of  claim 48 , further comprising generating test code associated with said customized description language using an automated process and based at least in part on the at least one customizable parameter.  
     
     
         50 . The method of  claim 48 , wherein the description language model includes both functional and structural description language descriptions for at least the processor core.  
     
     
         51 . The method of  claim 48 , wherein said instruction set comprises both base and extension instructions.  
     
     
         52 . The method of  claim 45 , wherein said at least one function comprises a digital signal processing (DSP) function.  
     
     
         53 . A user-configurable and extendable processing apparatus designed by the method comprising: 
 providing a software representation of a user-configurable and extendable processor core having an instruction set;    providing a software representation of a memory array;    providing a software representation of at least one macro function optimized for specific processing tasks;    providing software representation of at least one interface between said array and said at least one macro function; and    generating a design of said processing apparatus based at least in part on said software descriptions of said processor core, at least one macro function, memory array and at least one interface;    wherein said at least one macro function comprises an extension of said processor core.    
     
     
         54 . The apparatus of  claim 53 , wherein said at least one macro function is substantially under control of said processor core via one or more customized instructions within a base or extension instruction sets of said processor core.  
     
     
         55 . The apparatus of  claim 54 , wherein said one or more customized instructions act on data transferred to or out of said memory array in a pipelined fashion via said interface.  
     
     
         56 . The apparatus of  claim 53 , wherein said method of designing further comprises generating a description language model by at least: 
 receiving one or more inputs from a user for at least one customizable parameter of the processor core;    providing at least one prototype description of the processor core for which a model is being generated; and    generating through an automated process a description language model based on the least one customizable parameter and the at least one prototype description, said act of generating comprising modifying or substituting at least portions of said at least one prototype description.    
     
     
         57 . The apparatus of  claim 56 , further comprising generating test code associated with said customized description language using an automated process and based at least in part on the at least one customizable parameter.  
     
     
         58 . The apparatus of  claim 56 , wherein the description language model includes both functional and structural description language descriptions for at least the processor core.  
     
     
         59 . The apparatus of  claim 56 , wherein said instruction set comprises both base and extension instructions.  
     
     
         60 . The apparatus of  claim 53 , wherein said at least one function comprises a digital signal processing (DSP) function.