Customizable and Programmable Cell Array

Abstract

A semiconductor device may include a logic array having a multiplicity of inputs and a multiplicity of outputs and customized interconnections providing permanent direct interconnections among at least some of the multiplicity of inputs and at least some of the multiplicity of outputs.

1 . A method of building a library of cell functions to use in an array of programmable logic cells, said method comprising: 
 creating an initial library of cells;    synthesizing a high-level design to a gate-level design using said initial library of cells;    mapping said gate-level design into logic elements of said array of programmable logic cells, and    clustering said logic elements into cells of said array of programmable logic cells, wherein the cells of said array of programmable logic cells are incorporated into said library of cell functions.    
   
   
       2 . The method as in  claim 1 , wherein said programmable logic cells comprise at least one look up table, at least one multiplexer, at least two inverters, at least one simple logic gate, and at least one flip-flop, and 
 wherein said creating an initial library of cells comprises:    creating flip-flop functions using said multiplexers and said flip-flops in said logic cells;    creating inverter functions equivalent to said inverters in said logic cells;    creating logic functions to be implemented in said look up tables in said logic cells, and    creating logic functions to be implemented with said simple logic gates and said look up tables in said logic cells.    
   
   
       3 . A method of creating an eCell-netlist for an array of programmable logic cells, said logic cells having at least a look-up table and a multiplexer, the method comprising: 
 creating an initial library of cells;    synthesizing a high-level design to a gate-level design using said small library of cells;    mapping said gate-level design into logic elements of said array of programmable logic cells, including mapping a gate-level function into said multiplexer;    clustering said logic elements into cells of said array of programmable logic cells; and    generating an eCell-netlist.    
   
   
       4 . A method of creating an eCell-netlist for an array of programmable logic cells, said logic cells having at least a look-up table and a NAND gate, the method comprising: 
 creating an initial library of cells;    synthesizing a high-level design to a gate-level design using said small library of cells;    mapping said gate-level design into logic elements of said array of programmable logic cells, including mapping a gate-level function into said NAND gate;    clustering said logic elements into cells of said array of programmable logic cells; and    generating an eCell-netlist.    
   
   
       5 . A method of creating an eCell-netlist for an array of programmable logic cells, said logic cells having at least a look-up table and a multiplexer, the method comprising: 
 creating an initial library of cells;    synthesizing a high-level design to a gate-level design using said small library of cells;    mapping said gate-level design into logic elements of said array of programmable logic cells, including mapping a gate-level function of a critical path into said multiplexer;    clustering said logic elements into cells of said array of programmable logic cells; and    generating an eCell-netlist.    
   
   
       6 . A semiconductor device comprising: 
 a multiplicity of logic modules, each of said logic modules comprising a multiplicity of logic cells, said logic cells having a multiplicity of inputs and a multiplicity of outputs, each logic cell including at least one flip-flop and at least one multiplexer;    at least one standard metal layer; and    one or more metal connection layers overlying said multiplicity of logic modules to interconnect various inputs and outputs thereof in a customized manner.    
   
   
       7 . A semiconductor device as in  claim 6 , wherein said metal connection layers comprise strips for interconnecting various modules together in a customized manner.  
   
   
       8 . A semiconductor device as in  claim 7 , wherein said strips are customized by a single via layer.  
   
   
       9 . A method of providing information about a core, comprising: 
 providing one or more characteristics for determining said core's use in a design; and    providing data for integrating said core with said one or more characteristics into a design, wherein said data includes one or more indicia used to identify said core within a design.    
   
   
       10 . The method as in  claim 9 , wherein said one or more indicia are to identify mask layer data for fabricating said core embedded within a design.  
   
   
       11 . The method as in  claim 9 , wherein said one or more indicia are to reference library data, wherein library data referenced by said one or more indicia is combined with mask layer data to fabricate said core.  
   
   
       12 . A data bank including: 
 customizable and programmable portions of chip designs;    requirements of said portions of chip designs;    identification codes for providers of said portions of chip designs; and    cost estimates for said portions of chip designs;    wherein an owner of said data bank is able to provide to one or more customers access to said portions of chip designs in exchange for royalty payments, a portion of said payments to be transferred to said providers.    
   
   
       13 . A method of providing at least one core for integration into a system, the method comprising: 
 a) receiving, from a customer, a request for at least one core from a portal;    b) adding identification to at least one requested core, and transferring said at least one requested core with said identification to said customer; and    c) receiving a royalty corresponding to said at least one requested core.    
   
   
       14 . A method as in  claim 13 , wherein said receiving a royalty corresponding to at least one requested core comprises: 
 receiving a royalty determined by a foundry, the foundry receiving a system design including at least one requested core from said customer and extracting said identification from said system design.    
   
   
       15 . A method as in  claim 13 , wherein said portal is a web site.  
   
   
       16 . A method as in  claim 13 , wherein said cores are customizable and programmable.  
   
   
       17 . A method as in  claim 13 , wherein at least one requested core is transferred over the Internet to said customer for integration into a system design.  
   
   
       18 . A method as in  claim 13 , wherein said transferring at least one requested core includes: 
 selecting a most updated version of said at least one requested core; and    transferring said most updated version of said at least one requested core.    
   
   
       19 . A method as in  claim 13 , wherein said royalty is received from said customer.  
   
   
       20 . A method as in  claim 13 , wherein said royalty is received from a foundry used by said customer.  
   
   
       21 . A method of providing services relating to design and fabrication of a system, the method comprising: 
 a. receiving core data for at least one core for at least one portion of a system;    b. placing said core data into a data bank, along with one or more associated data selected from the group consisting of identification codes, requirements, and provider identification;    c. permitting a customer to review and select one or more cores from said core data bank to be integrated into a customer system design, and receiving said system design; and    d. extracting core identification data from said system design, accessing core fabrication and royalty information using said core identification data, calculating a cost of a system corresponding to said system design, providing information on said cost to said customer and transferring said system design to a foundry.    
   
   
       22 . A method as in  claim 21 , further comprising: 
 e. receiving fabricated systems, based on said system design, from said foundry; and    f. transferring said fabricated systems to said customer.    
   
   
       23 . A semiconductor device comprising: 
 a multiplicity of logic cells comprising at least one look-up table, wherein the contents of said look-up tables determine the function of said semiconductor device, and wherein the contents of at least one of said look-up tables is adapted to selectively observe and isolate a fault in a function of said semiconductor device.    
   
   
       24 . A method for verifying one or more faults to be detected by a set of test vectors with results on a semiconductor device comprising a multiplicity of logic cells comprising at least one look-up table, wherein the original contents of each of said at least one look-up table determines a function of said semiconductor device, and wherein said original contents of each of said at least one look-up table is modifiable to be equivalent to tying any of inputs and outputs of said at least one look-up table to one of two logic levels, the method comprising: 
 a) applying modifications to said original contents of at least one said look-up table,    b) applying said test vectors to said semiconductor device,    c) comparing results obtained in b) to a set of predetermined expected results for said test vectors, and    d) repeating a)-c) until all of said one or more faults have been applied to said semiconductor device.    
   
   
       25 . A method as in  claim 24 , wherein said modifications to said original contents of at least one said look-up table are equivalent to tying at least one of said at least one look-up table's inputs and outputs to one of two logic levels.