Vertical stacking of multiple integrated circuits including SOI-based optical components

Abstract

A vertical stack of integrated circuits includes at least one CMOS electronic integrated circuit (IC), an SOI-based opto-electronic integrated circuit structure, and an optical input/output coupling element. A plurality of metalized vias may be formed through the thickness of the stack so that electrical connections can be made between each integrated circuit. Various types of optical input/output coupling can be used, such as prism coupling, gratings, inverse tapers, and the like. By separating the optical and electrical functions onto separate ICs, the functionalities of each may be modified without requiring a re-design of the remaining system. By virtue of using SOI-based opto-electronics with the CMOS electronic ICs, a portion of the SOI structure may be exposed to provide access to the waveguiding SOI layer for optical coupling purposes.

1 . A vertically stacked arrangement of a plurality of integrated circuits, the arrangement comprising 
 a silicon-on-insulator (SOI)-based opto-electronic integrated circuit comprising at least a silicon substrate, an intermediate dielectric layer and a relatively thin silicon surface layer (SOI layer), with active and passive optical devices formed in at least the SOI layer;    at least one silicon-based electronic integrated circuit disposed to vertically stack with the SOI-based opto-electronic integrated circuit and provide electrical control signals thereto; and    an optical input/output coupling element disposed in conjunction with the SOI layer of the vertically stacked arrangement to couple optical signals into and out of the SOI-based opto-electronic integrated circuit.    
     
     
         2 . The vertically stacked arrangement as defined in  claim 1  wherein the optical input/output coupling element comprises a prism coupling element.  
     
     
         3 . The vertically stacked arrangement as defined in  claim 1  wherein the optical input/output coupling element comprises an optical grating for coupling signals into and out of the SOI layer.  
     
     
         4 . The vertically stacked arrangement as defined in  claim 1  wherein the optical input/output coupling element comprises an inverse taper coupling arrangement.  
     
     
         5 . The vertically stacked arrangement as defined in  claim 1  wherein the optical input/output coupling element comprises a three-dimensional adiabatically contoured coupling element to maintain the mode of the propagating optical signal.  
     
     
         6 . The vertically stacked arrangement as defined in  claim 1  wherein the plurality of integrated circuits are stacked such that the at least one silicon-based electronic integrated circuit is disposed as a bottom layer of the stack, with the SOI-based opto-electronic integrated circuit disposed over said at least one silicon-based electronic integrated circuit.  
     
     
         7 . The vertically stacked arrangement as defined in  claim 6  wherein a first plurality of metallic contacts is disposed on a top surface of the SOI-based opto-electronic integrated circuit and a second plurality of metallic contacts is disposed on a top surface of the at least one silicon-based electronic integrated circuit, with a plurality of metallized vias formed through the thickness of the SOI-based opto-electronic integrated circuit, the combination of the metallic contacts and metallized vias forming electrical signal paths through said vertically stacked arrangement.  
     
     
         8 . The vertically stacked arrangement as defined in  claim 6  wherein the SOI-based opto-electronic circuit is flip-chip bonded to the at least one silicon-based electronic integrated circuit.  
     
     
         9 . The vertically stacked arrangement as defined in  claim 6  wherein a plurality of metallic contacts are formed on a bottom surface of the at least one silicon-based electronic integrated circuit and a plurality of associated metallized vias are formed through the thickness of the at least one silicon-based electronic integrated circuit and the SOI-based opto-electronic circuit, the combination providing electrical signal paths through the vertically stacked arrangement.  
     
     
         10 . The vertically stacked arrangement as defined in  claim 9  wherein the plurality of metallic contacts on the bottom surface of the at least one silicon-based electronic integrated circuit are disposed to contact an associated printed wiring board.  
     
     
         11 . The vertically stacked arrangement as defined in  claim 1  wherein the plurality of integrated circuits are stacked such that the SOI-based opto-electronic circuit is disposed as the bottom, support integrated circuit, with the at least one silicon-based electronic integrated circuit and the optical input/output coupling element disposed at separate locations over the SOI layer of the SOI-based opto-electronic integrated circuit, the stacked arrangement further comprising a multi-layer dielectric/metal stack formed between the SOI layer and the at least one silicon-based electronic integrated circuit, the stack including a plurality of bond pads for providing electrical connections to external sources.  
     
     
         12 . The vertically stacked arrangement as defined in  claim 11  wherein the at least one silicon-based electronic integrated circuit is flip-chip bonded to the bond pads of the multi-layer stack.  
     
     
         13 . The vertically stacked arrangement as defined in  claim 11  wherein the at least one silicon-based electronic integrated circuit is wirebonded to the bond pads of the multi-layer stack.  
     
     
         14 . The vertically stacked arrangement as defined in  claim 11  wherein the at least one silicon-based electronic integrated circuit is attached to the SOI-based opto-electronic integrated circuit using a process selected from the group of: polymer bonding, low temperature plasma-activated direct bonding, eutectic bonding.  
     
     
         15 . The vertically stacked arrangement as defined in  claim 11  wherein the at least one silicon-based electronic integrated circuit comprises a plurality of separate silicon-based electronic integrated circuits.  
     
     
         16 . The vertically stacked arrangement as defined in  claim 15  wherein the plurality of silicon-based electronic integrated circuits are disposed at different locations over the surface of the SOI-based opto-electronic integrated circuit.  
     
     
         17 . The vertically stacked arrangement as defined in  claim 15  wherein the plurality of silicon-based electronic integrated circuits are disposed in a vertically stacked configuration over the dielectric layer.