Apparatus for controlling multi-word stack operations in digital data processors

Abstract

A digital data processor comprising a stack storage having a plurality of locations classified into two or more banks, and a stack pointer circuit pointing to one or more stack banks of the stack storage. The stack pointer circuit operates in response to decoding signals from an instruction decoder which decodes a current instruction to determine whether a one-word or a multi-word stack operation is desired.

1 . A hardware stack, comprising; 
 a stack storage comprising a plurality of banks each comprising storage locations;    an instruction decoder for decoding a stack-based instruction and generating a plurality of decoding signals, each of the plurality of decoding signals denoting one of a one-word push operation, a one-word pop operation, a two-word push operation and a two-word pop operation; and    a stack pointer circuit comprising a bank pointer for each bank, wherein each bank pointer points to a storage location of a corresponding bank, and wherein the stack pointer circuit is responsive to at lest one control signal to insert bank address data in at least two bank pointers to perform a multi-word push or multi-word pop operation.    
   
   
       2 . A digital data processor, comprising: 
 a stack storage including a plurality of locations, wherein each of the locations of said stack storage are assigned to one of a first bank and second bank;    a main stack pointer for pointing to a top location of said stack storage;    a first bank stack pointer for pointing to a top location of said first bank;    a second bank stack pointer for pointing to a top location of said second bank;    an instruction decoder for decoding a stack-based instruction and generating a plurality of decoding signals, each of the plurality of decoding signals denoting one of a one-word push operation, a one-word pop operation, a two-word push operation and a two-word pop operation; and    a stack pointer control logic circuit for controlling said first and second bank stack pointers in response to at lest one of the decoding signals to insert bank address data into the first and second bank stack pointers based on the content of the main stack pointer to perform a multi-word push or multi-word pop operation.    
   
   
       3 . The digital data processor of  claim 2 , wherein each location of the first and second banks is configured for storing a one-word item.  
   
   
       4 . The digital data processor of  claim 3 , wherein a two-word item is one of inserted into and removed from two adjacent locations at a given time.  
   
   
       5 . The digital data processor of  claim 4 , wherein said controller either increases of decreases the content of said main stack pointer by one when the decoding signals indicate a one-word stack operation, and wherein said controller either increases or decreases the content of said main stack pointer by two when the decoding signals indicate a two-word stack operation.  
   
   
       6 . The digital data processor of  claim 2 , wherein said stack storage comprises 2 n+1  locations, n being a positive integer, and wherein the first bank and the second bank each include 2 n  locations.  
   
   
       7 . The digital data processor of  claim 2 , wherein one of the first and second banks includes locations with addresses having a least significant bit of logic ‘0’ and the other of the first and second banks includes locations with addresses having a lest significant bit of logic ‘1’.  
   
   
       8 . A digital data processor, comprising; 
 a register set; and    a stack storage that communicates with the register set to perform a multi-word data push operation or a multi-word data pop operation.    
   
   
       9 . The digital data processor of  claim 8 , wherein the stack storage comprises a plurality of banks each comprising storage locations.  
   
   
       10 . The digital data processor of  claim 9 , comprising: 
 an instruction decoder for decoding a stack-based instruction and generating a plurality of decoding signals, each of the plurality of decoding signals denoting one of a the multi-word data push operation and the multi-word data pop operation; and    a stack pointer circuit comprising a bank pointer for each bank, wherein each bank pointer points to a storage location of a corresponding bank, and wherein the stack pointer circuit is responsive to at lest one control signal to insert bank address data in at least two bank pointers to perform a multi-word push or multi-word pop operation.    
   
   
       11 . The digital data processor of  claim 10 , wherein each location of the first and second banks is configured for storing a one-word item.  
   
   
       12 . A digital data processor, comprising; 
 a register set; and    a stack storage comprising a plurality of banks each comprising storage locations, wherein the stack storage transmits one of one-word data and two-word data to the register set, and wherein the stack storage comprises:    an instruction decoder for decoding a stack-based instruction and generating a plurality of decoding signals, each of the plurality of decoding signals denoting one of a one-word push operation, a one-word pop operation, a two-word push operation and a two-word pop operation; and    a stack pointer circuit comprising a bank pointer for each bank, wherein each bank pointer points to a storage location of a corresponding bank, and wherein the stack pointer circuit is responsive to at lest one control signal to insert bank address data in at least two bank pointers to perform a multi-word push or multi-word pop operation.    
   
   
       13 . A digital data processor, comprising: 
 a register set; and    a stack storage including a plurality of locations, wherein each of the locations of said stack storage are assigned to one of a first bank and second bank, wherein the stack storage transmits one of one-word data and two-word data to the register set, and wherein the stack storage comprises:    a main stack pointer for pointing to a top location of said stack storage;    a first bank stack pointer for pointing to a top location of said first bank;    a second bank stack pointer for pointing to a top location of said second bank;    an instruction decoder for decoding a stack-based instruction and generating a plurality of decoding signals, each of the plurality of decoding signals denoting one of a one-word push operation, a one-word pop operation, a two-word push operation and a two-word pop operation; and    a stack pointer control logic circuit for controlling said first and second bank stack pointers in response to at lest one of the decoding signals to insert bank address data into the first and second bank stack pointers based on the content of the main stack pointer to perform a multi-word push or multi-word pop operation.