Semiconductor memory device for low voltage

Abstract

A semiconductor memory device includes a first cell array including a plurality of unit cells and a bit line sense amplifying unit for sensing and amplifying data signals stored in the unit cells. Each unit cell is provided with a PMOS transistor and a capacitor. Therefore, the semiconductor memory device efficiently operates with low voltage without any degradation of operation speed.

1 . A semiconductor memory device, comprising: 
 a first cell array including a plurality of unit cells, each of which has a PMOS transistor and a capacitor; and    a bit line sense amplifying unit for sensing and amplifying data signals stored in the unit cells.    
   
   
       2 . The semiconductor memory device as recited in  claim 1 , wherein the PMOS transistor is turned on in response to a first low voltage having a lower voltage level than a ground voltage.  
   
   
       3 . The semiconductor memory device as recited in  claim 2 , wherein an absolute value of the first low voltage is greater than that of a threshold voltage of the PMOS transistor.  
   
   
       4 . The semiconductor memory device as recited in  claim 2 , wherein the PMOS transistor is turned on in case that a corresponding unit cell is activated and is turned off in case that the corresponding unit cell is inactivated.  
   
   
       5 . The semiconductor memory device as recited in  claim 4 , wherein the bit line sense amplifying unit amplifies the data signals stored in the unit cells based on a power supply voltage and a second low voltage which is higher than the first low voltage and lower than the ground voltage.  
   
   
       6 . The semiconductor memory device as recited in  claim 5 , wherein the first low voltage is about −2.0V and the second low voltage is about −0.5V.  
   
   
       7 . The semiconductor memory device as recited in  claim 1 , further comprising a second cell array sharing the bit line sense amplifying unit with the first cell array, wherein the second cell array includes a plurality of unit cells, each of which has a PMOS transistor and a capacitor.  
   
   
       8 . The semiconductor memory device as recited in  claim 7 , further comprising: 
 a first connecting PMOS transistor for connecting/disconnecting the first cell array to/from the bit line sense amplifying unit; and    a second connecting PMOS transistor for connecting/disconnecting the second cell array to/from the bit line sense amplifying unit.    
   
   
       9 . The semiconductor memory device as recited in  claim 8 , wherein the first and the second connecting PMOS transistors are turned on by a first negative voltage during a period where data signals stored in the plurality of unit cells loaded at a bit line pair and are turned on by a second negative voltage during the other periods, wherein an absolute value of the first negative voltage is greater than those of threshold voltages of the first and the second connecting PMOS transistors and an absolute value of the second negative voltage is substantially the same as those of the threshold voltages of the first and the second PMOS transistors.  
   
   
       10 . The semiconductor memory device as recited in  claim 1 , wherein the PMOS transistor is a finFET.  
   
   
       11 . The semiconductor memory device as recited in  claim 7 , wherein the bit line sense amplifying unit amplifies the data signals stored in the unit cells based on a power supply voltage and a low voltage which is lower than a ground voltage.  
   
   
       12 . The semiconductor memory device as recited in  claim 11 , wherein absolute values of the low voltage and the power supply voltage are the same.  
   
   
       13 . A semiconductor memory device, comprising: 
 a first cell array including a plurality of unit cells, each of which has a PMOS transistor and a capacitor, and a plurality of bit line pairs, wherein the first cell array provides a data signal stored in a unit cell selected from the unit cells to a first bit line pair selected from the bit line pairs, the first bit line pair containing a first bit line and a first bit line bar;    a bit line sense amplifier for sensing and amplifying a voltage difference between the first bit line and the first bit line bar after the data signal is provided to the first bit line pair;    a first reference cell block for transmitting a reference signal to the first bit line bar when the data signal is loaded on the first bit line and for transmitting the reference signal to the first bit line when the data signal is loaded on the first bit line bar; and    a first precharge block for equalizing voltage levels of the first bit line and the first bit line bar during a precharge period without supplying a precharge voltage to the first bit line pair, wherein the first bit line and the first bit line bar are in a floating state during the precharge period.    
   
   
       14 . The semiconductor memory device as recited in  claim 13 , wherein the first precharge block includes a PMOS transistor for connecting the first bit line and the first bit line bar during the precharge period.  
   
   
       15 . The semiconductor memory device as recited in  claim 13 , wherein the first reference cell block includes: 
 a first reference capacitor whose one terminal is coupled to a reference power supply terminal for providing the reference signal;    a first switch for connecting the other terminal of the first reference capacitor to the first bit line when the data signal is delivered to the first bit line bar; and    a second switch for connecting the other terminal of the first reference capacitor to the first bit line bar when the data signal is delivered to the first bit line.    
   
   
       16 . The semiconductor memory device as recited in  claim 15 , wherein a capacitance of the first reference capacitor is substantially the same as that of the capacitor of the unit cell in the first cell array.  
   
   
       17 . The semiconductor memory device as recited in  claim 15 , wherein each of the first and the second switches includes a PMOS transistor.  
   
   
       18 . The semiconductor memory device as recited in  claim 16 , wherein the reference power supply terminal provides one of a ground voltage, a half of a power supply voltage, and the power supply voltage.  
   
   
       19 . The semiconductor memory device as recited in  claim 15 , wherein the number of the first reference capacitors included in the first reference cell block corresponds to the number of the bit line pairs included in the first cell array.  
   
   
       20 . The semiconductor memory device as recited in  claim 13 , wherein the bit line sense amplifier performs sensing and amplifying operation based on a first low voltage which is lower than a ground voltage.  
   
   
       21 . The semiconductor memory device as recited in  claim 20 , wherein the PMOS transistor in the unit cell is turned on in response to a second low voltage which is lower than the first low voltage.  
   
   
       22 . The semiconductor memory device as recited in  claim 20 , wherein an absolute value of the first low voltage is greater than that of a threshold voltage of the PMOS transistor in the unit cell.  
   
   
       23 . The semiconductor memory device as recited in  claim 21 , wherein the PMOS transistor in the unit cell is turned on in response to the second low voltage when the unit cell is activated and turned off in response to a power supply voltage when the unit cell is inactivated.  
   
   
       24 . The semiconductor memory device as recited in  claim 13 , wherein the bit line sense amplifier amplifies the data signal based on a power supply voltage and a low voltage which is lower than a ground voltage.  
   
   
       25 . The semiconductor memory device as recited in  claim 24 , wherein absolute values of the low voltage and the power supply voltage are the same.  
   
   
       26 . The semiconductor memory device as recited in  claim 13 , further comprising a first connection block configured between the bit line sense amplifier and the first precharge block to connect/disconnect the first bit line pair to/from the bit line sense amplifier.  
   
   
       27 . The semiconductor memory device as recited in  claim 26 , wherein the first connection block includes: 
 a first connecting PMOS transistor for connecting the first bit line and the bit line sense amplifier in response to a first connection control signal; and    a second connecting PMOS transistor for connecting the first bit line bar and the bit line sense amplifier in response to the first connection control signal.    
   
   
       28 . The semiconductor memory device as recited in  claim 27 , wherein the first and the second connecting PMOS transistors are turned on by a first negative voltage during a period where the data signal is loaded on the first bit line or the first bit line bar and are turned on by a second negative voltage during the other periods, wherein an absolute value of the first negative voltage is greater than those of threshold voltages of the first and the second connecting PMOS transistors and an absolute value of the second negative voltage is substantially the same as those of the threshold voltages of the first and the second PMOS transistors.  
   
   
       29 . The semiconductor memory device as recited in  claim 27 , further comprising a first auxiliary bit line sense amplifier for amplifying and maintaining a line voltage of the first bit line pair to a ground voltage, wherein the line voltage is a voltage of the first bit line or that of the first bit line bar whose voltage level is lower than the other.  
   
   
       30 . The semiconductor memory device as recited in  claim 29 , wherein the first auxiliary bit line sense amplifier includes: 
 a first NMOS transistor whose first terminal receives a signal which is enabled when the bit line sense amplifier is activated, the other terminal is coupled to the first bit line connected between the first cell array and the first connection block, and gate is coupled to the first bit line bar connected between the first cell array and the first connection block; and    a second NMOS transistor whose first terminal receives the signal which is enabled when the bit line sense amplifier is activated, the other terminal is coupled to the first bit line bar connected between the first cell array and the first connection block, and gate is coupled to the first bit line connected between the first cell array and the first connection block.    
   
   
       31 . The semiconductor memory device as recited in  claim 29 , further comprising: 
 a second cell array including a plurality of unit cells, each of which has a PMOS transistor and a capacitor, and a plurality of bit line pairs, wherein the second cell array provides a data signal stored in a unit cell selected from the unit cells to a second bit line pair selected from the bit line pairs, the second bit line pair containing a second bit line and a second bit line bar;    a second connection block for connecting/disconnecting the second line pair to/from the bit line sense amplifier;    a second reference cell block for transmitting a reference signal to the second bit line bar when the data signal is loaded on the second bit line and for transmitting the reference signal to the second bit line when the data signal is loaded on the second bit line bar; and    a second precharge block for equalizing voltage levels of the second bit line and the second bit line bar during the precharge period without supplying a precharge voltage to the second bit line pair.    
   
   
       32 . The semiconductor memory device as recited in  claim 31 , wherein the second reference cell block and the second precharge block are activated when the second connection block is activated to thereby make the second bit line pair maintain the precharge voltage level.  
   
   
       33 . The semiconductor memory device as recited in  claim 31 , wherein the second connection block includes: 
 a third connecting PMOS transistor for connecting the second bit line and the bit line sense amplifier in response to a second connection control signal; and    a fourth connecting PMOS transistor for connecting the second bit line bar and the bit line sense amplifier in response to the second connection control signal.    
   
   
       34 . The semiconductor memory device as recited in  claim 33 , wherein the third and the fourth connecting PMOS transistors are turned on by a third negative voltage during a period where the data signal is loaded on the second bit line or the second bit line bar and are turned on by a fourth negative voltage during the other periods, wherein an absolute value of the third negative voltage is greater than those of threshold voltages of the third and the fourth connecting PMOS transistors and an absolute value of the fourth negative voltage is substantially the same as those of the threshold voltages of the third and the fourth PMOS transistors.  
   
   
       35 . The semiconductor memory device as recited in  claim 31 , further comprising a second auxiliary bit line sense amplifier for amplifying and maintaining a line voltage of the second bit line pair to the ground voltage, where the line voltage is a voltage of the second bit line or that of the second bit line bar whose voltage level is lower than the other.  
   
   
       36 . The semiconductor memory device as recited in  claim 35 , wherein the second auxiliary bit line sense amplifier includes: 
 a first NMOS transistor whose first terminal receives a signal which is enabled when the bit line sense amplifier is activated, the other terminal is coupled to the second bit line connected between the second cell array and the second connection block, and gate is coupled to the second bit line bar connected between the second cell array and the second connection block; and    a second NMOS transistor whose first terminal receives the signal which is enabled when the bit line sense amplifier is activated, the other terminal is coupled to the second bit line bar connected between the second cell array and the second connection block, and gate is coupled to the second bit line connected between the second cell array and the second connection block.    
   
   
       37 . The semiconductor memory device as recited in  claim 31 , wherein the second precharge block includes a PMOS transistor for connecting the second bit line and the second bit line bar during the precharge period.  
   
   
       38 . The semiconductor memory device as recited in  claim 31 , wherein the bit line sense amplifier includes: 
 a first sense amplifying PMOS transistor whose gate is connected to the first bit line bar by the first connection unit and to the second bit line bar by the second connection unit, wherein one terminal of the first sense amplifying PMOS transistor is coupled to a power supply voltage and the other terminal is coupled to the first bit line by the first connection unit and to the second bit line by the second connection unit;    a second sense amplifying PMOS transistor whose gate is connected to the first bit line by the first connection unit and to the second bit line by the second connection unit, wherein one terminal of the second sense amplifying PMOS transistor is coupled to the power supply voltage and the other terminal is connected to the first bit line bar by the first connection unit and to the second bit line bar by the second connection unit;    a first sense amplifying NMOS transistor whose gate is connected to the first bit line bar by the first connection unit and to the second bit line bar by the second connection unit, wherein one terminal of the first sense amplifying NMOS transistor is coupled to the first low voltage and the other terminal is connected to the first bit line by the first connection unit and to the second bit line by the second connection unit; and    a second sense amplifying NMOS transistor whose gate is connected to the first bit line by the first connection unit and to the second bit line by the second connection unit, wherein one terminal of the second sense amplifying NMOS transistor is coupled to the first low voltage and the other terminal is connected to the first bit line bar by the first connection unit and to the second bit line bar by the second connection unit.    
   
   
       39 . The semiconductor memory device as recited in  claim 38 , further comprising a data input/output block for outputting a data signal sensed and amplified by the bit line sense amplifier to a data line and delivering a data signal inputted through the data line to the bit line sense amplifier.  
   
   
       40 . The semiconductor memory device as recited in  claim 39 , wherein the data input/output block includes: 
 a first input/output MOS transistor whose gate receives an input/output control signal, first terminal is connected to the first and the second bit lines, and second terminal is coupled to a first data line; and    a second input/output MOS transistor whose gate receives the input/output control signal, first terminal is connected to the first and the second bit line bars, and second terminal is coupled to a second data line.    
   
   
       41 . The semiconductor memory device as recited in  claim 13 , wherein the PMOS transistor in the unit cell is a finFET.  
   
   
       42 . A method for driving a semiconductor memory device including a plurality of unit cells and a plurality of bit line pairs, comprising: 
 turning on a PMOS transistor included in a unit cell selected from the unit cells;    transmitting a data signal stored in the unit cell to a bit line in a corresponding bit line pair; and    sensing and amplifying a voltage difference between the bit line and a bit line bar of the corresponding bit line pair based on a first low voltage which is lower than a ground voltage.    
   
   
       43 . The method as recited in  claim 42 , wherein the bit line receiving a high data is amplified as a power supply voltage and the bit line bar is amplified as the first low voltage.  
   
   
       44 . The method as recited in  claim 43 , wherein absolute values of the first low voltage and the power supply voltage are the same.  
   
   
       45 . The method as recited in  claim 42 , wherein the PMOS transistor is turned on in response to a second low voltage which is lower than the first low voltage.  
   
   
       46 . The method as recited in  claim 45 , wherein an absolute value of the second low voltage is greater than that of a threshold voltage of the PMOS transistor.  
   
   
       47 . The method as recited in  claim 42 , further comprising performing a clamping operation to thereby prevent the first low voltage from being transmitted to the bit line pair connected to the unit cell during sensing and amplifying a voltage difference between the bit line and a bit line bar.  
   
   
       48 . The method as recited in  claim 47 , further comprising amplifying a lower voltage level of the bit line pair as the ground voltage level.  
   
   
       49 . The method as recited in  claim 47 , further comprising outputting a data signal sense and amplified by a bit line sense amplifying unit through a data line in response to a read command.  
   
   
       50 . The method as recited in  claim 47 , further comprising replacing a data signal latched by a bit line sense amplifying unit with a data signal transmitted through a data line in response to a write command.  
   
   
       51 . The method as recited in  claim 47 , further comprising restoring a data signal latched by a bit line sense amplifying unit into the unit cell.  
   
   
       52 . The method as recited in  claim 42 , wherein sensing and amplifying a voltage difference between the bit line and a bit line bar includes: 
 supplying a bit line bar of a second cell array adjacent to a first cell array including the unit cell corresponds to the data signal with a reference signal;    sensing and amplifying a voltage difference between the data signal and the reference signal.    
   
   
       53 . The method as recited in  claim 52 , further comprising: 
 disconnecting bit lines configured in the first cell array among bit lines connected to a bit line sense amplifying unit from the bit line sense amplifying unit;    disconnecting bit line bars configured in the second cell array among bit line bars connected to the bit line sense amplifying unit from the bit line sense amplifying unit; and    amplifying voltages of the disconnected bit lines and bit line bars as the ground voltage.    
   
   
       54 . The method as recited in  claim 52 , further comprising without supplying a precharge voltage during a precharge period floating voltage levels of the bit line and the bit line bar.  
   
   
       55 . A method for driving a semiconductor memory device having a folded bit line structure and including a bit line sense amplifier, a first cell array and a second cell array sharing the bit line sense amplifier with the first cell array, comprising: 
 connecting a first bit line pair configured in the first cell array to the bit line sense amplifier and disconnecting a second bit line pair configured in the second cell array from the bit line sense amplifier;    activating a PMOS transistor of a unit cell selected from a plurality of unit cells configured in the first cell array to thereby transmit a data signal stored in the unit cell to a first bit line of the first bit line pair, wherein each unit cell has a PMOS transistor and a capacitor;    transmitting a reference signal to a first bit line bar of the first bit line pair; and    sensing and amplifying a voltage difference between the first bit line and the first bit line bar based on a power supply voltage and a first low voltage lower than a ground voltage.    
   
   
       56 . The method as recited in  claim 55 , wherein one of the first bit line and the first bit line bar which receives a high level data is amplified as the power supply voltage and the other is amplified as the first low voltage.  
   
   
       57 . The method as recited in  claim 56 , wherein absolute values of the first low voltage and the power supply voltage are the same.  
   
   
       58 . The method as recited in  claim 55 , wherein the PMOS transistor is turned on in response to a second low voltage which is lower than the first low voltage.  
   
   
       59 . The method as recited in  claim 58 , wherein an absolute value of the second low voltage is greater than that of a threshold voltage of the PMOS transistor.  
   
   
       60 . The method as recited in  claim 55 , further comprising equalizing and floating the first bit line pair and the second bit line pair after disconnecting the first bit line pair from the bit line sense amplifier.  
   
   
       61 . The method as recited in  claim 55 , wherein sensing and amplifying a voltage difference between the first bit line and the first bit line bar includes performing a clamping operation to thereby prevent the first low voltage from being transmitted to the first bit line pair connected to the unit cell.  
   
   
       62 . The method as recited in  claim 55 , further comprising amplifying a lower voltage level of the first bit line pair as the ground voltage.  
   
   
       63 . The method as recited in  claim 55 , further comprising outputting a data signal sensed and amplified and latched by the bit line sense amplifier through a data line in response to a read command.  
   
   
       64 . The method as recited in  claim 55 , further comprising replacing a data signal sensed and amplified by the bit line sense amplifier with a data signal transmitted through a data line in response to a write command.  
   
   
       65 . The method as recited in  claim 55 , further comprising restoring a data signal sensed and amplified by the bit line sense amplifier into the unit cell.  
   
   
       66 . The method as recited in  claim 55 , wherein charge quantity of the reference signal has a value between charge quantity when the data signal transmitted to the first bit line is ‘0’ and a charge quantity when the data signal transmitted to the first bit line is ‘1’.  
   
   
       67 . The method as recited in  claim 66 , wherein the charge quantity of the reference signal is half of a larger charge quantity of the charge quantity when the data signal transmitted to the first bit line is ‘0’ and the charge quantity when the data signal transmitted to the first bit line is ‘1’.  
   
   
       68 . The method as recited in  claim 56 , further comprising precharging the second bit line pair while the first bit line pair is connected to the bit line sense amplifier.  
   
   
       69 . The method as recited in  claim 68 , wherein the second bit line pair is precharged by using the reference signal.  
   
   
       70 . A semiconductor memory device, comprising: 
 a first cell array including a plurality of unit cells each of which has a PMOS transistor and a capacitor and transmitting a first data signal stored in a unit cell selected from the plurality of unit cells to a first bit line;    a second cell array including a plurality of unit cells each of which has a PMOS transistor and a capacitor and transmitting a second data signal stored in a unit cell selected from the plurality of the unit cells to a second bit line;    a bit line sense amplifier for sensing and amplifying a voltage difference between the first bit line and the second bit line;    a reference cell block for transmitting a reference signal to the second bit line when the first data signal is loaded on the first bit line and transmitting the reference signal to the first bit line when the second data signal is loaded on the second bit line; and    a precharge block for equalizing the first bit line and the second bit line without supplying the first and the second bit lines with a precharge voltage during a precharge period.    
   
   
       71 . The semiconductor memory device as recited in  claim 70 , wherein the precharge block includes a PMOS transistor for electrically connecting the first and the second bit lines during the precharge period.  
   
   
       72 . The semiconductor memory device as recited in  claim 70 , wherein the reference cell block includes: 
 a reference capacitor whose one terminal is coupled to a reference power supply terminal for providing the reference signal;    a first switch for connecting the other terminal of the reference capacitor to the first bit line when the second data signal is delivered to the second bit line; and    a second switch for connecting the other terminal of the reference capacitor to the reference power supply terminal during the precharge period.    
   
   
       73 . The semiconductor memory device as recited in  claim 72 , wherein a capacitance of the reference capacitor is substantially the same as that of the capacitor in the unit cell.  
   
   
       74 . The semiconductor memory device as recited in  claim 73 , wherein each of the first and the second switches is a PMOS transistor.  
   
   
       75 . The semiconductor memory device as recited in  claim 73 , wherein the reference power supply terminal provides one of a ground voltage, half of a power supply voltage, and the power supply voltage.  
   
   
       76 . The semiconductor memory device as recited in  claim 72 , wherein the number of the reference capacitors included in the first reference cell block corresponds to the number of the bit line pairs included in the first cell array.  
   
   
       77 . The semiconductor memory device as recited in  claim 70 , wherein the bit line sense amplifier performs an amplifying operation based on a first low voltage which is lower than a ground voltage.  
   
   
       78 . The semiconductor memory device as recited in  claim 77 , wherein the PMOS transistor included in the unit cell is turned on in response to a second low voltage which is lower than the first low voltage.  
   
   
       79 . The semiconductor memory device as recited in  claim 78 , wherein an absolute value of the first low voltage is greater than that of a threshold voltage of the PMOS transistor.  
   
   
       80 . The semiconductor memory device as recited in  claim 79 , wherein the PMOS transistor is turned on in response to the second low voltage when the unit cell is activated and turned off in response to a power supply voltage when the unit cell is inactivated.  
   
   
       81 . The semiconductor memory device as recited in  claim 70 , wherein the bit line sense amplifier amplifies the first or the second data signal based on a power supply voltage and a low voltage which is lower than a ground voltage.  
   
   
       82 . The semiconductor memory device as recited in  claim 81 , wherein absolute values of the low voltage and the power supply voltage are the same.  
   
   
       83 . The semiconductor memory device as recited in  claim 77 , further comprising: 
 a first connection block configured between the bit line sense amplifier and the first cell array for preventing the first low voltage from being supplied to the first bit line; and    a second connection block configured between the bit line sense amplifier and the second cell array for preventing the first low voltage from being supplied to the second bit line.    
   
   
       84 . The semiconductor memory device as recited in  claim 83 , wherein the first connection block includes a first connecting PMOS transistor for connecting the first bit line and the bit line sense amplifier.  
   
   
       85 . The semiconductor memory device as recited in  claim 84 , wherein the second connection block includes a second connecting PMOS transistor for connecting the second bit line and the bit line sense amplifier.  
   
   
       86 . The semiconductor memory device as recited in  claim 85 , wherein the first and the second connecting PMOS transistors are turned on by a first negative voltage during a period where a data signal is loaded on one of the first and the second bit line and are turned on by a second negative voltage during the other periods, wherein an absolute value of the first negative voltage is greater than those of a threshold voltages of the first and the second connecting PMOS transistors and an absolute value of the second negative voltage is substantially the same as those of the threshold voltages of the first and the second PMOS transistors.  
   
   
       87 . The semiconductor memory device as recited in  claim 85 , further comprising a first auxiliary bit line sense amplifier for amplifying and maintaining the lower one of the first bit line between the first cell array and the first connection block and the second bit line between the second cell array and the second connection block as the ground voltage level.  
   
   
       88 . The semiconductor memory device as recited in  claim 87 , wherein the first auxiliary bit line sense amplifier includes: 
 a first NMOS transistor whose first terminal receives the signal which is enabled when the bit line sense amplifier is activated, the other terminal is coupled to the first bit line connected between the first cell array and the first connection block, and gate is coupled to the second bit line connected between the second cell array and the second connection block; and    a second NMOS transistor whose first terminal receives the signal which is enabled when the bit line sense amplifier is activated, the other terminal is coupled to the second bit line connected between the second cell array and the second connection block, and gate is coupled to the first bit line connected between the first cell array and the first connection block.    
   
   
       89 . The semiconductor memory device as recited in  claim 70 , wherein the bit line sense amplifier includes: 
 a first sense amplifying PMOS transistor whose gate is connected to the second bit line by the second connection block, wherein one terminal of the first sense amplifying PMOS transistor is coupled to the power supply voltage and the other terminal is coupled to the first bit line;    a second sense amplifying PMOS transistor whose gate is connected to the first bit line by the first connection unit, wherein one terminal of the second sense amplifying PMOS transistor is coupled to the power supply voltage and the other terminal is connected to the first bit line by the first connection block;    a first sense amplifying NMOS transistor whose gate is connected to the second bit line by the second connection block, wherein one terminal of the first sense amplifying NMOS transistor is coupled to the first low voltage and the other terminal is connected to the first bit line by the first connection block; and    a second sense amplifying NMOS transistor whose gate is connected to the first bit line by the first connection unit, wherein one terminal of the first sense amplifying NMOS transistor is coupled to the first low voltage and the other terminal is connected to the second bit line by the second connection block.    
   
   
       90 . The semiconductor memory device as recited in  claim 89 , further comprising a data input/output block for outputting a data signal sensed and amplified by the bit line sense amplifier through a data line and for delivering a data signal inputted from the data line to the bit line sense amplifier.  
   
   
       91 . The semiconductor memory device as recited in  claim 90 , wherein the data input/output block includes: 
 a first input/output MOS transistor whose gate receives an input/output control signal, first terminal is connected to a common node of the first sense amplifying PMOS transistor and the first sense amplifying NMOS transistor, and second terminal is coupled to a first data line; and    a second input/output MOS transistor whose gate receives the input/output control signal, first terminal is connected to the common node of the second sense amplifying PMOS transistor and the secondt sense amplifying NMOS transistor, and second terminal is coupled to a second data line.    
   
   
       92 . The semiconductor memory device as recited in  claim 70 , wherein the PMOS transistor in the unit cell is a finFET.