Reduced hardware network adapter and communication method

Abstract

The present invention provides a network interface adapter for connecting a client computer to a computer network that includes a reduced hardware media access controller (MAC) coupled through a physical interface (PHY) to the network physical link. A significant portion of the MAC functionality is implemented as software within the processor of the host client computer. The hardware portion of the preferred MAC implementation provides memory for buffering communications between the PHY and the client computer. The preferred hardware aspects of a MAC in accordance with the present invention also includes a register interface for register-driven communications between the hardware portion of the MAC and the software portions of the MAC implemented within the client computer. By implementing most of the MAC functionality in software within the host computer, the preferred MAC provides lower cost, lower power consumption, and generally greater flexibility.

1 - 17 . (canceled)  
   
   
       18 . A system comprising: 
 a hardware media access controller, the hardware media access controller including a memory to buffer data transferred between a physical interface to a network and a computer, and the hardware media access controller including a register interface; and    a memory storing media access control software that if executed by a processor of the computer causes the processor to perform one or more media access control communications functions.    
   
   
       19 . The system of  claim 18 , wherein the software comprises software that if executed by the processor causes the processor to perform one or more IEEE 802.3 functions.  
   
   
       20 . The system of  claim 18 , wherein the software comprises software that if executed by the processor causes the processor to perform one or more network interface control functions.  
   
   
       21 . The system of  claim 18 , wherein the software comprises software that if executed by the processor causes the processor to detect an error condition.  
   
   
       22 . The system of  claim 18 , wherein the software comprises software that if executed by the processor causes the processor to perform an error handling function.  
   
   
       23 . The system of  claim 22 , wherein the software comprises software that if executed by the processor causes the processor to perform the error handling function by performing a backoff algorithm.  
   
   
       24 . The system of  claim 22 , wherein the software comprises software that if executed by the processor causes the processor to perform the error handling function by flushing the memory of the hardware media access controller of data.  
   
   
       25 . The system of  claim 18 , wherein the software comprises software that if executed by the processor causes the processor to handle interrupts and data transfer.  
   
   
       26 . The system of  claim 18 , wherein the software comprises software that if executed by the processor causes the processor to process a data packet including detecting a frame preamble, and checking a length of a frame.  
   
   
       27 . The system of  claim 18 , wherein the software comprises software that if executed by the processor causes the processor to evaluate a frame using frame check sequence data.  
   
   
       28 . The system of  claim 27 , wherein the software comprises software that if executed by the processor causes the processor to evaluate the frame using the frame check sequence data by performing a polynomial division using a protocol defined check polynomial.  
   
   
       29 . The system of  claim 18 , wherein the software comprises software that if executed by the processor causes the processor to perform filtering to detect whether an address of a packet is relevant to the computer.  
   
   
       30 . The system of  claim 18 , wherein the memory comprises a memory of the computer.  
   
   
       31 . The system of  claim 18 , wherein a size of the memory is based on a typical latency delay of the computer.  
   
   
       32 . A system comprising: 
 a computer including a processor, a DRAM memory, and a bus;    an adapter including, 
 a physical interface to couple to a network, and  
 a hardware media access controller coupled to the physical interface and to the bus, the hardware media access controller including a memory to buffer data that is transferred between the physical interface and the computer, and the hardware media access controller including a register interface; and  
   media access control software stored within the DRAM memory that if executed by the processor of the computer causes the processor to perform one or more media access control communications functions.    
   
   
       33 . The system of  claim 32 , wherein the software comprises software that if executed by the processor causes the processor to perform one or more IEEE 802.3 functions.  
   
   
       34 . The system of  claim 32 , wherein the software comprises software that if executed by the processor causes the processor to perform one or more network interface control functions.  
   
   
       35 . The system of  claim 32 , wherein the software comprises software that if executed by the processor causes the processor to detect an error condition and perform an error handling function.  
   
   
       36 . The system of  claim 32 , wherein the software comprises software that if executed by the processor causes the processor to process a data packet including detecting a frame preamble, and checking a length of a frame.  
   
   
       37 . The system of  claim 32 , wherein the software comprises software that if executed by the processor causes the processor to evaluate a frame using frame check sequence data.  
   
   
       38 . A memory storing media access control software that if executed by a processor of a computer causes the processor to: 
 perform one or more media access control communications functions.    
   
   
       39 . The memory of  claim 38 , wherein the software comprises software that if executed by the processor causes the processor to perform one or more IEEE 802.3 functions.  
   
   
       40 . The memory of  claim 38 , wherein the software comprises software that if executed by the processor causes the processor to perform one or more network interface control functions.  
   
   
       41 . The memory of  claim 38 , wherein the software comprises software that if executed by the processor causes the processor to detect an error condition and perform an error handling function.  
   
   
       42 . The memory of  claim 38 , wherein the software comprises software that if executed by the processor causes the processor to process a data packet including detecting a frame preamble, and checking a length of a frame.  
   
   
       43 . The memory of  claim 38 , wherein the software comprises software that if executed by the processor causes the processor to evaluate a frame using frame check sequence data.  
   
   
       44 . A method comprising: 
 installing a card in a computer, the card including a physical interface to a network and a hardware media access controller; and    installing media access control software within a memory of the computer, the media access control software including software that if executed results in a processor of the computer performing one or more media access control communications functions.    
   
   
       45 . The method of  claim 44 , wherein said installing the software comprises installing software that if executed results in the processor evaluating a frame using frame check sequence data.