Method for data communication

Abstract

In order to enable high speed, high bandwidth data transfer between two ASIC devices, for example in a backplane, a wide parallel input data word is divided into a smaller number of words, and each smaller word is converted to serial form and then transmitted over a respective sub-link at a high clock rate relative to the system clock. At the receiving side, the clock is recovered from the serial words, and the serial words are converted back to parallel form. An alignment process is then carried out, firstly involving detecting the positions of the bits of the words and then storing the words in a buffer FIFO register. The words are clocked out of the FIFO register in synchronism under control of the system clock once it is detected that valid words are received in the FIFO registers.

1 . A method for transmitting data over a communication link between a first integrated circuit having a system clock and a second integrated circuit, comprising the steps of: 
 a. responsive to the system clock, generating a transfer clock at a high rate relative to the system clock;    b. sending one or more bit alignment code words to initialize the communication link;    c. dividing an input word into a plurality of smaller words; and    d. transmitting the plurality of smaller words over corresponding serial sub-links in response to the transfer clock.    
   
   
       2 . The method of  claim 1 , further comprising the step of: 
 e. transmitting a CRC code word at predetermined intervals.    
   
   
       3 . A method for receiving data transmitted over a communication link having a plurality of serial sub-links at an integrated circuit having a system clock, comprising the steps of: 
 a. receiving a plurality of serial data words over the plurality of serial sub-links;    b. responsive to the plurality of serial data words, generating a low speed clock with a frequency nominally equal to the system clock;    c. storing the received serial data words for each sub-link in a plurality of buffer memories corresponding respectively to each sub-link; and    d. reading the buffer memories in synchronism under control of the system clock in order to reconstitute each data word in parallel form.    
   
   
       4 . The method according to  claim 3 , wherein the buffer memories are FIFO registers.  
   
   
       5 . The method according to  claim 4 , wherein the step c. of storing received data words comprises the step of: 
 e. addressing the buffer memories by changing only one bit of the address for each incremental address.    
   
   
       6 . The method according to  claim 5 , wherein the step d. of reading the buffer memories comprises the steps of: 
 f. comparing a predetermined bit of the address of each FIFO; and    g. generating a trigger signal to actuate a state machine to cause reading of the FIFO registers.    
   
   
       7 . A method for receiving data transmitted over a communication link having a plurality of serial sub-links at an integrated circuit having a system clock, comprising the steps of: 
 a. receiving a plurality of serial data words over the plurality of serial sub-links;    b. storing the received serial data words for each sub-link in a plurality of serial-to-parallel registers corresponding to the serial sub-links;    c. responsive to the plurality of serial data words, generating a low speed clock with a frequency nominally equal to the system clock;    d. detecting one or more edges of the received serial data words;    e. based on the one or more detected edges, aligning the low speed clock with the plurality of serial data words; and    f. applying the low speed clock to the plurality of serial-to-parallel registers for clocking out parallel words from the plurality of serial-to-parallel registers.    
   
   
       8 . The method according to  claim 7 , further comprising the step of: 
 g. storing the received bit alignment words in a bit alignment register in order to locate the position of the bits in the plurality of serial-to-parallel registers.    
   
   
       9 . The method according to  claim 8 , further comprising the steps of: 
 h. generating a CRC code word in response to the received data; and    i. checking a received CRC code word against the generated CRC code word.    
   
   
       10 . A method for communicating data over a communication link between a first integrated circuit having a first system clock and a second integrated circuit having a second system clock, comprising the steps of: 
 a. responsive to the first system clock, generating a transfer clock at a high rate relative to the first system clock;    b. sending one or more bit alignment code words from the first integrated circuit to the second integrated circuit to initialize the communication link;    c. dividing an input word into a plurality of smaller words;    d. transmitting the plurality of smaller words from the first integrated circuit to the second integrated circuit over a corresponding plurality of serial sub-links in response to the transfer clock;    e. receiving, at the second integrated circuit, the plurality of smaller words over the plurality of serial sub-links;    f. responsive to the plurality of serial data words, generating a low speed clock with a frequency nominally equal to the second system clock;    g. storing the received serial data words for each sub-link in a plurality of buffer memories corresponding respectively to each sub-link; and    h. reading the buffer memories in synchronism under control of the second system clock in order to reconstitute each data word in parallel form.