Flexible processing hardware architecture

Abstract

A flexible, reconfigurable processing system architecture allows for the implementation of a variety of processing system configurations to be implemented on a single device, which is preferably a PCI bus add-in extension board with an attached daughter card attached and electrically connected thereto through a PCI Mezzanine type connector, and which is plugged into a personal computer PCI expansion slot. The architecture uses the PCI bus, for example, as the local CPU bus for an embedded processor, which not only allows for flexibility in system configuration but also allows PCI devices to be hidden from the host CPU to allow for proper system startup. The architecture further permits an embedded processing CPU to be re-booted when the secondary PCI bus host bus bridge fails to respond without affecting host CPU or other secondary PCI bus peripheral devices. The architecture provides a method of loading an embedded system CPU's local memory with operating system and diagnostic code without the use of ROM or FLASH memory. A system and method of reserving memory is also disclosed which utilizes a dummy or surrogate board with little of no functionality but which has a class code of a common device such as an Ethernet card. The primary system BIOS will read the class code and reserve memory based on the surrogate card. The driver of the non-standard card such as an embedded processor, can then use the memory space allocated to the surrogate card by the BIOS.

1 . A vision processing system comprising: 
 a host processing system including a host central processing unit (CPU) and a host peripheral component interconnect (PCI) bus coupled to said host CPU; and    at least one vision processing subsystem implemented as a PCI add-in extension board coupled to said host processing system, said at least one vision processing subsystem including a local PCI bus, a peripheral bus bridge coupling said local PCI bus to said host PCI bus, at least one PCI device coupled to said local PCI bus, and means for hiding said at least one PCI device from said host processing system.    
   
   
       2 . The vision processing system of  claim 1  wherein said at least one vision processing subsystem includes a plurality of vision processing subsystems implemented on a plurality of PCI add-in extension boards.  
   
   
       3 . The vision processing system of  claim 1  wherein said at least one vision processing subsystem includes a digitizer subsystem.  
   
   
       4 . The vision processing system of  claim 3  wherein said PCI device includes a camera interface in said digitizer subsystem.  
   
   
       5 . The vision processing system of  claim 1  wherein said at least one vision processing subsystem includes a vision processing accelerator subsystem.  
   
   
       6 . The vision processing system of  claim 5  wherein said PCI device includes a processing accelerator in said vision processing accelerator subsystem.  
   
   
       7 . The vision processing system of  claim 1  wherein said at least one vision processing subsystem includes an embedded CPU subsystem having an embedded CPU.  
   
   
       8 . The vision processing system of  claim 7  wherein said PCI device includes a display controller in said embedded CPU subsystem.  
   
   
       9 . The vision processing system of  claim 7  wherein said PCI device includes a host bus bridge coupled to said embedded CPU in said embedded CPU subsystem.  
   
   
       10 . The vision processing system of  claim 1  wherein said means for hiding said PCI device includes a connection of an identification selection (IDSEL) line of said PCI device to a PCI address line of said local PCI bus in a range of AD [31:16] and a means for temporarily disabling said IDSEL line.  
   
   
       11 . The vision processing system of  claim 1  wherein said means for hiding said PCI device includes means for controlling a reset release signal and identification selection (IDSEL) signal to temporarily disable said PCI device from said local PCI bus.  
   
   
       12 . The vision processing system of  claim 1  wherein said means for hiding said PCI device includes a complex programmable logic device (CPLD) and a state machine for controlling a reset release and for controlling identification selection (IDSEL) connection sequencing to temporarily disable said PCI device from said local PCI bus.  
   
   
       13 . The vision processing system of  claim 7  further including a back-door signal between said peripheral bus bridge and said embedded CPU subsystem, for resetting said embedded CPU subsystem if said embedded CPU subsystem locks up.