Asynchronous, multi-rail, asymmetric-phase, static digital logic with completion detection and method for designing the same

Abstract

A method of converting a Boolean logic circuit into an asynchronous multi-rail circuit is provided. A Boolean logic circuit is converted into a first multi-rail circuit using at least Shannon's expansion. The first multi-rail circuit is technology mapped into a second multi-rail circuit. Completion detection circuitry is added which receives the primary outputs of the second multi-rail circuit.

1 . A method of converting a Boolean logic circuit into an asynchronous multi-rail circuit, comprising: 
 converting the Boolean logic circuit into a first multi-rail circuit using at least Shannon's expansion;    technology mapping the first multi-rail circuit into a second multi-rail circuit;    adding completion detection circuitry which receives the primary outputs of the second multi-rail circuit.    
   
   
       2 . The method of  claim 1 , wherein as a result of said technology mapping the second multi-rail circuit is a combination of positive logic and negative logic.  
   
   
       3 . The method of  claim 1 , wherein as a result of said adding the completion detection circuitry which receives only the primary outputs of the second multi-rail circuit.  
   
   
       4 . The method of  claim 1 , wherein as a result of said adding the completion detection circuitry does receives any intermediate signals from the second multi-rail circuit.  
   
   
       5 . The method of  claim 1 , wherein as a result of said adding the completion detection circuitry does receives any primary input signals from the second multi-rail circuit.  
   
   
       6 . The method of  claim 1 , further comprising optimizing the first multi-rail circuit before said technology mapping.  
   
   
       7 . The method of  claim 1 , further comprising optimizing the second multi-rail circuit before said adding.  
   
   
       8 . The method of  claim 1 , further comprising optimizing at least the second multi-rail circuit after said adding.  
   
   
       9 . The method of  claim 1 , further comprising: 
 dividing the second multi-rail circuit into m slices;    adding reset circuitry to at least a second slice of said m slices through an mth slice of said m slices, said circuitry being configured to receive a reset signal, such that a reset signal will simultaneously be applied to at least a second through an mth slice of said m slices.    
   
   
       10 . The method of  claim 9 , wherein the reset signal is output by the completion detection circuitry.  
   
   
       11 . The method of  claim 1 , further comprising: 
 propogating the completion detection signal upstream for use in the second multi-rail circuit; and    adding a delay to the completion detection signal;    propagating the delayed completion detection signal upstream of the second multi-rail circuit.