Finite impulse response filter

Abstract

A system for determining the depth of a fluid in a storage tank. The depth of the fluid is determined after the detection of a pulsed wave that is reflected from the top surface of the fluid. The system includes a transducer, an analog-to-digital converter, and a filter. The transducer is configured to sense the reflected pulsed wave and to generate an analog input signal that corresponds to the reflected pulsed wave. The analog-to-digital converter is coupled to the transducer, and configured to convert the analog input signal into a digital input signal. The filter is coupled to the analog-to-digital converter. The filter includes a finite impulse response filter that is configured to receive the digital input signal and to generate a digital output signal.

1 .- 32 . (canceled)  
   
   
       33 . A finite impulse response filter comprising: 
 a. an n-stage register, where n is an integer that is greater than one;    b. a subtractor having a first input terminal that is coupled to one of the stages of the n-stage shift register, a second input terminal, and an output terminal;    c. an adder having a first input terminal that is coupled to another of the stages of the n-stage shift register, a second input terminal, and an output terminal that is coupled to the subtractor's second input terminal; and    d. a storage register having an input terminal that is coupled to the subtractor's output terminal, and an output terminal that is coupled to the adder's second input terminal.    
   
   
       34 . A finite impulse response filter comprising: 
 a. a two-stage shift register;    b. a first subtractor having two input terminals and an output terminal, where each of the first subtractor input terminals is coupled to one of the stages of the two-stage shift register;    c. an n/ 2 -stage shift register, where n is an even integer greater than or equal to four, having an input terminal that is coupled to the output terminal of the first subtractor;    d. a second subtractor having a first input terminal that is coupled to the output terminal of the first subtractor, a second input terminal that is coupled to the n/ 2 th stage of the n/ 2 -stage shift register, and an output terminal;    e. an adder having a first input terminal that is coupled to the second subtractor's output terminal, a second input terminal, and an output terminal; and    f. a storage register having an input terminal that is coupled to the adder's output terminal, and an output terminal that is coupled to the adder's second input terminal.    
   
   
       35 . A finite impulse response filter configured to receive a digital input signal and to produce a digital output signal, the finite impulse response filter comprising: 
 a. an input terminal that receives a digital input signal;    b. a shift register that stores a succession of values based on the digital input signal; and    c. a circuit that generates a filtered digital output signal based on ( 1 ) the previous value of the filtered digital output signal, ( 2 ) the current value of the digital input signal, and ( 3 ) a value stored in the shift register.    
   
   
       36 . The finite impulse response filter defined in  claim 35 , wherein: 
 a. the shift register includes n stages, where n is an integer that is greater than one; and    b. the circuit comprises 
 i. a subtractor that is coupled to the n-stage shift register,  
 ii. an adder that is coupled to both the n-stage shift register and the subtractor, and  
 iii. a storage register that is coupled to both the adder and the subtractor.  
   
   
   
       37 . The finite impulse response filter defined in  claim 36 , wherein: 
 a. the subtractor has a first input terminal that is coupled to one of the stages of the n-stage shift register, a second input terminal, and an output terminal;    b. the adder has a first input terminal that is coupled to another of the stages of the n-stage shift register, a second input terminal, and an output terminal that is coupled to the subtractor's second input terminal; and    c. the storage register has an input terminal that is coupled to the subtractor's output terminal, and an output terminal that is coupled to the adder's second input terminal.    
   
   
       38 . The finite impulse response filter defined in  claim 35 , wherein: 
 a. the shift register has n/ 2  stages, where n is an even integer greater than or equal to four; and    b. the finite impulse response filter further comprises 
 i. a two-stage shift register,  
 ii. a first subtractor coupled to the two-stage shift register and to the n/ 2 -stage shift register,  
 iii. a second subtractor coupled both to the first subtractor and to the n/ 2 -stage shift register,  
 iv. an adder coupled to the second subtractor, and  
 V. a storage register coupled to the adder.  
   
   
   
       39 . The finite impulse response filter defined in  claim 38 , wherein: 
 a. the first subtractor has two input terminals and an output terminal, and each of the first subtractor's input terminals is coupled to one of the stages of the two-stage shift register;    b. the n/ 2 -stage shift register has an input terminal that is coupled to the output terminal of the first subtractor;    c. the second subtractor has a first input terminal that is coupled to the output terminal of the first subtractor, a second input terminal that is coupled to the n/ 2 th stage of the n/ 2 -stage shift register, and an output terminal;    d. the adder has a first input terminal that is coupled to the second subtractor's output terminal, a second input terminal, and an output terminal; and    e. the storage register has an input terminal that is coupled to the adder's output terminal, and an output terminal that is coupled to the adder's second input terminal.    
   
   
       40 . The finite impulse response filter defined in  claim 38 , wherein the finite impulse response filter is configured to calculate a digital output signal at time t 0 , Output (t 0 ), based on ( 1 ) the digital input signal at time to, Input (t 0 ); ( 2 ) the digital output signal at time t 1 , Output (t 1 ); and ( 3 ) a data value in the final stage of the n/ 2 -stage shift register at time t 0 , X n−2 (t 0 )−X n−1 (t 0 ), where t 0  is the time at the current clock cycle and t 1  was the time at the previous clock cycle, and Output (t 0 ) is calculated based on the following equation:  
       Output (t 0 )=Input (t 0 )−Input (t 1 )−X n−2 (t 0 )+X n−1 (t 0 )+Output (t 1 ).  
   
   
       41 . The finite impulse response filter defined in  claim 38 , wherein: 
 a. the two-stage shift register is configured to store the current value of the digital input signal, Input (t 0 ), and the previous value of the digital input signal, Input (t 1 );    b. the first subtractor is configured to determine the difference between Input (t 0 ) and Input (t 0 ), to produce a difference value X 0 −X 1 ;    c. the n/ 2 -stage shift register is configured to store previous n/ 2  successive difference values produced by the first subtractor;    d. the second subtractor is configured to determine the difference between the current difference value X 0 −X 1  and the difference value stored in the final stage of the n/ 2 -stage shift register, X n−2 −X n−1 , to produce an output value;    e. the adder is configured to determine the sum of the current output value produced by the second subtractor and the previous value of the digital output signal, Output (t 1 ), to produce the current value of the digital output signal, Output (t 0 ); and    f. the storage register is configured to store the previous value of the digital output signal, Output (t 1 ), and provide it to the adder.    
   
   
       42 . The finite impulse response filter defined in  claim 38 , wherein the finite impulse response filter is configured to calculate a digital output signal at time t 0 , Output (t 0 ), based on ( 1 ) the difference between the digital input signal at time t 0 , Input (t 0 ), and the digital input signal at time t 1 , Input (t 1 ); ( 2 ) a digital output signal at time t 1 , Output (t 1 ); and ( 3 ) the difference between the digital input signal at time t n−2 , Input (t n−2 ), and the digital input signal at time t n− , Input (t n−1 ), which is stored in the final stage of the n/ 2 -stage shift register at time t 0 .  
   
   
       43 . A complex digital filter configured to produce a filtered digital output signal based on a sinusoidal input signal having a prescribed nominal frequency, the complex digital filer comprising: 
 a. an input circuit that samples the sinusoidal input signal at twice the prescribed nominal frequency, to produce first and second digital input signals that are  90  degrees out of phase with each other;    b. a first finite impulse response filter comprising 
 i. a first shift register that stores a succession of values based on the first digital input signal, and  
 ii. a first processor circuit that generates a first digital output signal based on ( 1 ) the previous value of the first digital output signal, ( 2 ) the current value of the first digital input signal, and ( 3 ) a value stored in the first shift register;  
   c. a second finite impulse response filter comprising 
 i. a second shift register that stores a succession of values based on the second digital input signal, and  
 ii. a second processor circuit that generates a second digital output signal based on ( 1 ) the previous value of the second digital output signal, ( 2 ) the current value of the second digital input signal, and ( 3 ) a value stored in the second shift register; and  
   d. an output circuit responsive to the first and second digital output signals, to produce a filtered digital output signal.    
   
   
       44 . The complex digital filter defined in  claim 43 , wherein the output circuit calculates a square root of a sum of squares value of the first and second digital output signals.  
   
   
       45 . The complex digital filter defined in  claim 43 , wherein the output circuit calculates an approximate value of a square root of a sum of squares value by adding the larger of an absolute value of the first digital output signal and an absolute value of the second digital output signal to  3 / 8  times the smaller of the absolute value of the first digital output signal and the absolute value of the second digital output signal.  
   
   
       46 . The complex digital filter defined in  claim 45 , wherein the approximate value of the square root of the sum of squares value is calculated by: 
 a. shifting the n/ 2 -stage shift register to the right twice for the first or second finite impulse response filter that has the smaller absolute value of output signal;    b. adding an output of the twice right-shifted, n/ 2 -stage shift register to the output of the first or second finite impulse response filter that has the larger absolute value, resulting in a first added value;    c. shifting the n/ 2 -stage shift register having the smaller absolute value of output signal once more to the right; and    d. adding the output of the thrice right-shifted, n/ 2 -stage shift register to the first added value.    
   
   
       47 . The complex digital filter defined in  claim 43 , wherein the output circuit is configured to determine the phase difference between the digital input signal and coefficients that define the filter.  
   
   
       48 . The complex digital filter defined in  claim 43 , wherein: 
 a. the first and second shift registers each include n stages, where n is an integer that is greater than one; and    b. the first and second processor circuits each comprise 
 i. a subtractor that is coupled to the n-stage shift register,  
 ii. an adder that is coupled to both the n-stage shift register and the subtractor, and  
 iii. a storage register that is coupled to both the adder and the subtractor.  
   
   
   
       49 . The complex digital filter defined in  claim 43 , wherein: 
 a. the first and second shift registers each have n/ 2  stages, where n is an even integer than or equal to four; and    b. the first and second finite impulse response filter each further comprise 
 i. a two-stage shift register,  
 ii. a first subtractor coupled to the two-stage shift register and to the n/ 2 -stage shift register,  
 iii. a second subtractor coupled both to the first subtractor and to the n/ 2 -stage shift register,  
 iv. an adder coupled to the second subtractor, and  
 v. a storage register coupled to the adder.