Memory buffers for merging local data from memory modules

Abstract

An integrated circuit to serialize local data and selectively merge it with serialized feed-through data into a serial data stream output that includes a parallel-in-serial-out (PISO) shift register, a multiplexer, and a transmitter. The PISO shift register serializes parallel data on a local data bus into serialized local data. The multiplexer selectively merges serialized local data and feed-through data into a serial data stream. The transmitter drives the serial data stream onto a serial data link. In another embodiment of the invention, a method for a memory module includes receiving an input serial data stream; merging local frames of data and feed-through frames of data together into an output serial data stream in response to a merge enable signal; and transmitting the output serial data stream on a northbound data output to a next memory module or a memory controller. Other embodiments of the invention are disclosed and claimed.

1 . An integrated circuit comprising: 
 a serial input/output interface with one or more lanes, each lane including 
 a first parallel-in-serial-output (PISO) shift register having a parallel input coupled to a local data bus, a clock input coupled to a first clock signal, a load/shift-bar input coupled to a load signal, the first PISO shift register to serialize parallel data on the local data bus into serialized local data on a first serial output;  
 a first multiplexer having a first data input coupled to the first serial output, a second data input to receive feed-through data, a select input coupled to a local data select signal, the first multiplexer to selectively merge the serialized local data and the feed-through data into a serial data stream on a multiplexed output responsive to the local data select signal; and  
 a transmitter having an input coupled to the multiplexed output to receive the serial data stream, the transmitter to drive the serial data stream onto a serial data link.  
   
     
     
         2 . The integrated circuit of  claim 1 , wherein 
 the feed-through data is two bits wide,    the parallel input of the first PISO shift register is at least six bits wide and the serial output of the first PISO shift register is two bits wide,    the first multiplexer is a two bit bus multiplexer and the serial data stream at the multiplexed output is two bits wide, and    the transmitter receives the two bit serial data stream and serializes it onto the serial data link as a single bit serial data stream.    
     
     
         3 . The integrated circuit of  claim 1 , wherein 
 each lane further includes 
 a second multiplexer having a first data input to receive resynchronized data, a second data input to receive re-sampled data, a select input coupled to a local clock mode signal, the second multiplexer to select the re-sampled data or the resynchronized data as the feed-through data in response to the local clock mode signal.  
   
     
     
         4 . The integrated circuit of  claim 1 , wherein 
 each lane further includes    control logic coupled to the first multiplexer and the first PISO shift register, the control logic to receive the first clock signal and a merge enable signal, the control logic to generate the local data select signal to merge the serialized local data and the feed-through data into the serial data stream in response to the merge enable signal and the first clock signal.    
     
     
         5 . The integrated circuit of  claim 4 , wherein 
 the control logic has merge control logic that includes 
 a second multiplexer having a first data input coupled to the merge enable signal and a select input coupled to the load signal,  
 a D-type flip-flop coupled to the second multiplexer, the D-type flip-flop having a data input coupled to an output of the second multiplexer, and a clock input coupled to the first clock signal, and a data output coupled to the select input of the first multiplexer and a second data input of the second multiplexer, the D-type flip-flop to register the merge enable signal in response to the load signal and the first clock signal to generate the local data select signal on the data output, and  
 wherein the second multiplexer to recirculate the local data select signal into the data input of the D-type flip-flop in response to an inverse of the load signal.  
   
     
     
         6 . The integrated circuit of  claim 1 , wherein 
 the parallel input of the first PISO shift register is coupled to one half of bits of the local data bus,    and each lane further includes 
 a second parallel-in-serial-output (PISO) shift register having a parallel input coupled to another half of the bits of the local data bus, a clock input coupled to the first clock signal, a load/shift-bar input coupled to the load signal, a second serial output coupled to a serial input of the first PISO shift register, the second PISO shift register to serialize parallel data on the another half of the bits of the local data bus into serialized local data on the second serial output to couple into the serial input of the first PISO shift register.  
   
     
     
         7 . The integrated circuit of  claim 6 , wherein 
 each lane further includes 
 a bus multiplexer coupled between the local bus and the first PISO shift register, the bus multiplexer having a first data input coupled to the one half of the bits of the local data bus, a second data input coupled to the another half of the bits of the local data bus, a multiplexed output coupled to the parallel input of the first PISO shift register, and a select input coupled to a data bus select signal, the bus multiplexer to selectively couple the one half of the bits of the local data bus or the another half of the bits of the local data bus into the parallel input of the first PISO shift register in response to the data bus select signal.  
   
     
     
         8 . The integrated circuit of  claim 7 , wherein 
 each lane further includes    control logic coupled to the multiplexer and the first PISO shift register, the control logic to receive the first clock signal, a mode select signal, and a merge enable signal, the control logic to generate the local data select signal to merge the serialized local data and the feed-through data into the serial data stream in response to the merge enable signal and the first clock signal, the control logic to further generate the data bus select signal in response to the mode select signal.    
     
     
         9 . The integrated circuit of  claim 8 , wherein 
 the load signal is an early load pulse signal that is coupled into the load/shift-bar bar input of the second PISO shift register, and    the control logic has merge control logic that includes 
 a second multiplexer having a first data input coupled to the merge enable signal and a select input coupled to the early load pulse signal,  
 a first D-type flip-flop coupled to the second multiplexer, the first D-type flip-flop having a data input coupled to an output of the second multiplexer, and a clock input coupled to the first clock signal, and a data output coupled to the select input of the first multiplexer and a second data input of the second multiplexer, the first D-type flip-flop to register the merge enable signal in response to the early load pulse signal and the first clock signal to generate the local data select signal on the data output, and  
 wherein the second multiplexer to recirculate the local data select signal into the data input of the first D-type flip-flop in response to the early load pulse signal being a logical low and to couple the merge enable signal into the first D-type flip-flop in response to the early load pulse signal being a logical high;  
 the control logic further has mode control logic that includes  
 a third multiplexer having a first data input coupled to the early load pulse signal,  
 a second D-type flip-flop coupled to the third multiplexer, the second D-type flip-flop having a data input coupled to an output of the third multiplexer, a clock input coupled to the first clock signal, a clear input coupled to an inverted bus mode signal, and a data output coupled to the select input of the bus multiplexer and a second data input of the third multiplexer, the second D-type flip-flop to generate the data bus select signal on the data output in response to the inverted bus mode signal, the early load pulse signal, and the first clock signal,  
 an OR gate having a first input coupled to the early load pulse signal and a second input coupled to a late load pulse signal, the OR gate to logically OR the early load pulse signal and the late load pulse signal,  
 an AND gate having a first input coupled to an output of the OR gate, a second input coupled to a bus mode signal, an output coupled to a select input of the third multiplexer,  
 an inverter having an input coupled to the bus mode signal and an output coupled to the clear input of the second D-type flip-flop, the inverter to generate the inverted bus mode signal in response to the bus mode signal,  
 a fourth multiplexer having a first data input coupled to the early load pulse signal, a second data input coupled to the output of the OR gate, a control input coupled to the bus mode signal, and a multiplexed output coupled to the load/shift-bar bar input of the first PISO shift register,  
 wherein the third multiplexer to recirculate the data bus select signal into the data input of the second D-type flip-flop in response to the inverted bus mode signal, and  
 wherein the fourth multiplexer to selectively couple the early load pulse signal or both the early load pulse signal and the late load pulse signal into the load/shift-bar bar input of the first PISO shift register.  
   
     
     
         10 . The integrated circuit of  claim 9 , wherein 
 the integrated circuit is a buffer integrated circuit,    the local bus is twelve bits wide, and    the bus multiplexer in each lane selectively couples a lower six bits of the local bus into the first PISO shift register and an upper six bits of the local bus into the first PISO shift register in response to the data bus select signal.    
     
     
         11 . A method for a memory module comprising: 
 receiving an input serial data stream representing feed-through frames of data interspersed between idle frames of data;    merging local frames of data and the feed-through frames of data together into an output serial data stream in response to a merge enable signal without decoding the input serial data stream; and    transmitting the output serial data stream on a northbound data output to a next memory module or a memory controller.    
     
     
         12 . The method of  claim 11 , wherein 
 the local frames of data are merged into the output serial data stream by replacing idle frames of data in the input serial data stream.    
     
     
         13 . The method of  claim 11 , wherein 
 the receiving of the input serial data stream includes 
 sampling the bits of data in the input serial data stream.  
   
     
     
         14 . The method of  claim 11 , wherein 
 the receiving of the input serial data stream includes 
 re-synchronizing the bits of data in the input serial data stream.  
   
     
     
         15 . The method of  claim 11 , wherein 
 the merging of local frames of data and the feed-through frames of data together includes 
 serializing parallel bits of the local frames of data into serial bits of data and  
 multiplexing the serial bits of data of the local frames of data and serial bits of the feed-through frames of data into serial bits of the output serial data stream in response to the merge enable signal.  
   
     
     
         16 . The method of  claim 11 , wherein 
 a local frame of data is selectively received in parallel over a local bus in six bit or twelve bit packets in response to a bus mode signal.    
     
     
         17 . A system comprising: 
 a processor to execute instructions and process data;    a memory controller coupled to the processor, the memory controller to receive write memory instructions with write data from the processor and to receive read memory instructions from the processor and supply read data to the processor;    at least one bank of memory coupled to the memory controller, the at least one bank of memory including one or more memory modules, each of the one or more memory modules including 
 a buffer integrated circuit and  
 at least one memory integrated circuit; and  
   wherein the buffer integrated circuit includes    a southbound serial input/output interface with one or more serial lanes to receive the write data from the memory controller, and    a northbound serial input/output interface with one or more serial lanes of a northbound serial input and a northbound serial output, the northbound serial input/output interface to transmit the read data to the memory controller, the northbound serial input/output interface including for each serial lane 
 a parallel-to-serial converter having a parallel input coupled to parallel bits of a local data bus, a clock input coupled to a first clock signal, a load/shift-bar input coupled to a load signal, the parallel-to-serial converter to serialize the parallel bits of data on the local data bus into serialized local data on a first serial output, and  
 a first multiplexer having a first data input coupled to the serial output of the parallel-to-serial converter, a second data input to receive serial feed-through data from the northbound serial input, and a select input coupled to a local data select signal, the multiplexer to selectively merge the serialized local data and the serial feed-through data into a serial data stream on the northbound serial output in response to the local data select signal.  
   
     
     
         18 . The system of  claim 17 , wherein 
 each serial lane of the northbound serial input/output interface further includes    a transmitter having an input coupled to the multiplexed output of the first multiplexer to receive the serial data stream, the transmitter to drive the serial data stream onto the northbound serial data output towards the memory controller.    
     
     
         19 . The system of  claim 17 , wherein 
 for each bank of memory, the memory controller includes 
 a northbound serial input interface to receive one or more lanes of serial data from the one or more memory modules, and  
 a southbound serial output interface to transmit one or more lanes of serial data to the one or more memory modules.  
   
     
     
         20 . The system of  claim 17 , wherein 
 each serial lane of the northbound serial input/output interface further includes    control logic coupled to the multiplexer and the first parallel-to-serial converter, the control logic to receive the first clock signal and a merge enable signal, the control logic to generate the local data select signal to merge the serialized local data and the serial feed-through data into the serial data stream in response to the merge enable signal and the first clock signal.    
     
     
         21 . The system of  claim 17 , wherein 
 each serial lane of the northbound serial input/output interface further includes 
 a second multiplexer having a first data input to receive resynchronized serial data, a second data input to receive re-sampled serial data, a select input coupled to a local clock mode signal, the second multiplexer to select the re-sampled serial data or the resynchronized serial data as the serial feed-through data in response to the local clock mode signal.  
   
     
     
         22 . A buffered memory module comprising: 
 a printed circuit board with an edge connection;    a plurality of memory integrated circuits coupled to the printed circuit board; and    a buffer integrated circuit coupled to the printed circuit board, the buffer integrated circuit further electrically coupled to the plurality of memory integrated circuits and the edge connection, the buffer integrated circuit having a southbound input/output interface and a northbound input/output interface, the northbound input/output interface includes data merge logic with a plurality of merge logic slices for a plurality of lanes of serial data streams, each merge logic slice including 
 a first parallel-in-serial-output (PISO) shift register having a parallel input coupled to a local data bus, a clock input coupled to a first clock signal, a load/shift-bar input coupled to a first load signal, the first PISO shift register to serialize parallel data on the local data bus into serialized local data on a first serial output; and  
 a first multiplexer having a first data input coupled to the first serial output of the first PISO shift register, a second data input to receive serialized feed-through data, a select input coupled to a local data select signal, the first multiplexer to selectively merge the serialized local data and the serialized feed-through data into a serial data stream on a multiplexed output in response to the local data select signal.  
   
     
     
         23 . The buffered memory module of  claim 22 , wherein 
 the northbound input/output interface further includes    a plurality of transmitters each having an input coupled to a corresponding output of the first multiplexer in each merge logic slice, the plurality of transmitters to receive the serial data stream and drive it onto a serial data link.    
     
     
         24 . The buffered memory module of  claim 22 , wherein 
 each merge logic slice further includes 
 a second multiplexer having a first data input to receive resynchronized serial data, a second data input to receive re-sampled serial data, a select input coupled to a local clock mode signal, the second multiplexer to select the re-sampled serial data or the resynchronized serial data as the serialized feed-through data in response to the local clock mode signal.  
   
     
     
         25 . The buffered memory module of  claim 24 , wherein 
 each merge logic slice further includes 
 control logic coupled to the first multiplexer and the first PISO shift register, the control logic to receive the first clock signal and a merge enable signal, the control logic to generate the local data select signal to merge the serialized local data and the serialized feed-through data into the serial data stream in response to the merge enable signal and the first clock signal.  
   
     
     
         26 . A memory system comprising: 
 a plurality of buffered memory modules daisy chained together to form a bank of memory, each buffered memory module including    a plurality of memory integrated circuits; and    a buffer integrated circuit coupled to the plurality of memory integrated circuits, the buffer integrated circuit including 
 a southbound input/output serial interface to receive and retransmit southbound serial data from a memory controller or a prior buffered memory module to a next buffered memory module,  
 a northbound input/output serial interface to receive northbound serial data from at least one buffered memory module as serialized feed-through data and retransmit it towards the memory controller, the northbound input/output serial interface to serialize local data from the plurality of memory integrated circuits and merge it into a northbound serial data stream with the serialized feed-through data without decoding the received northbound serial data, the northbound input/output serial interface further to transmit the northbound serial data stream, including the serialized feed-through data and the serialized local data, towards the memory controller,  
 a write data first-in-first-out (FIFO) buffer coupled to the southbound input/output serial interface, the write data FIFO buffer to store write data from the southbound input/output serial interface addressed to the buffered memory module by a write command,  
 a memory input/output interface coupled to the plurality of memory integrated circuits and the write data FIFO buffer, the memory input/output interface to transfer write data stored in the write data FIFO buffer into at least one of the plurality of memory integrated circuits,  
 a read data FIFO buffer coupled to the northbound input/output serial interface and the memory input/output interface, the read data FIFO buffer to store read data from at least one of the plurality of memory integrated circuits as the local data addressed from the buffered memory module by a read command, and  
 wherein the memory input/output interface to transfer read data from the at least one of the plurality of memory integrated circuits into the read data FIFO buffer.  
   
     
     
         27 . The memory system of  claim 26 , further comprising 
 the memory controller coupled to at least one of the plurality of buffered memory modules, the memory controller including 
 a southbound output serial interface to transmit the southbound serial data stream to the at least one of the plurality of buffered memory modules and  
 a northbound input serial interface to receive the northbound serial data stream from the at least one of the plurality of buffered memory modules.  
   
     
     
         28 . The memory system of  claim 26 , wherein 
 the northbound input/output serial interface of the buffer integrated circuit includes 
 a third FIFO buffer,  
 data merge logic coupled to the third FIFO buffer, the data merge logic having a plurality of merge logic slices each including 
 a first parallel-in-serial-output (PISO) shift register having a parallel input coupled to a local data bus, a clock input coupled to a first clock signal, a load/shift-bar input coupled to a first load signal, the first PISO shift register to serialize parallel data on the local data bus into serialized local data on a first serial output, and  
 a first multiplexer having a first data input coupled to the first serial output of the first PISO shift register, a second data input to receive serialized feed-through data, a select input coupled to a local data select signal, the first multiplexer to selectively merge the serialized local data and the serialized feed-through data into a serial data stream on a multiplexed output in response to the local data select signal, and  
 
 a plurality of transmitters coupled to the data merge logic, each of the plurality of transmitters having an input coupled to a corresponding output of the first multiplexer in each merge logic slice, the plurality of transmitters to receive the serial data stream and drive it onto a serial data link.  
   
     
     
         29 . The memory system of  claim 28 , wherein 
 each merge logic slice of the data merge logic further includes 
 a second multiplexer having a first data input to receive resynchronized serial data, a second data input to receive re-sampled serial data, a select input coupled to a local clock mode signal, the second multiplexer to select the re-sampled serial data or the resynchronized serial data as the serialized feed-through data in response to the local clock mode signal.  
   
     
     
         30 . The memory system of  claim 28 , wherein 
 each merge logic slice of the data merge logic further includes 
 control logic coupled to the first multiplexer and the first PISO shift register, the control logic to receive the first clock signal and a merge enable signal, the control logic to generate the local data select signal to merge the serialized local data and the serialized feed-through data into the serial data stream in response to the merge enable signal and the first clock signal.