US2006197089A1PendingUtilityA1
Semiconductor device and its manufacturing method
Est. expiryMar 3, 2025(expired)· nominal 20-yr term from priority
Inventors:Ching-Yeh KuoTsung-Chi ChengYu-Chou LeeYea-Chung ShihWen-Kuang TsaoHsiang-Hsien ChungHung-Yi HsuJui-Chung Chang
H10D 30/0312H10D 30/67H10D 30/6743H10D 30/6739H10D 30/6737H10D 30/031
35
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Claims
Abstract
A semiconductor device and its manufacturing method are disclosed. The nitrogen flow is gradually changed to form a semiconductor device with a gate or a source/drain having a nitrified gradient layer structure. Different extents of nitrification inside the nitrified gradient layer structure provide protection and buffering to prevent the undercut after etching due to different materials in the multilayer structure or the interface effect.
Claims
exact text as granted — not AI-modified1 . A semiconductor device, comprising:
a substrate; and a gate formed on said substrate, wherein said gate comprises nitrogen whose concentration has a gradient distribution.
2 . The semiconductor device of claim 1 , wherein said substrate is a glass substrate.
3 . The semiconductor device of claim 1 , wherein said concentration of nitrogen in said gate increases from the near to the far of said substrate.
4 . The semiconductor device of claim 1 , wherein said gate comprises a metal and nitrides of said metal.
5 . The semiconductor device of claim 4 , wherein said metal is selected from the group consisting of Al, Cu, Ag, Mo, Cr, Ti, and their alloys, and AlNd.
6 . A semiconductor device, comprising:
a substrate; a gate formed on said substrate; a semiconductor layer formed on said gate; a source/drain formed on said semiconductor layer respectively, wherein the concentration of nitrogen in said source and said drain has a gradient distribution; and a channel formed between said source and said drain.
7 . The semiconductor device of claim 6 , wherein said substrate is a glass substrate.
8 . The semiconductor device of claim 6 , wherein said concentration of nitrogen in said gate has a gradient distribution.
9 . The semiconductor device of claim 6 , wherein said concentration of nitrogen in said gate increases from the near to the far of said substrate.
10 . The semiconductor device of claim 6 , wherein said gate comprises a metal and nitrides of metal.
11 . The semiconductor device of claim 10 , wherein said metal is selected from the group consisting of Al, Cu, Ag, Mo, Cr, Ti, and their alloys, and AlNd.
12 . The semiconductor device of claim 6 , wherein said concentration of nitrogen in said source/drain increases from the far and the near of said substrate.
13 . The semiconductor device of claim 6 , wherein said source/drain comprises a metal and nitrides of said metal.
14 . The semiconductor device of claim 13 , wherein said metal is selected from the group consisting of Al, Cu, Ag, Mo, Cr, Ti, and their alloys, and AlNd.
15 . The semiconductor device of claim 6 further comprising a gate insulating layer between said gate and said semiconductor layer.
16 . The semiconductor device of claim 6 further comprising an ohmic contact layer formed on said semiconductor layer.
17 . The semiconductor device of claim 6 further comprising a passivation layer formed on said substrate covering said gate, said semiconductor layer, and said source/drain.
18 . The semiconductor device of claim 17 further comprising a contact hole formed in said passivation layer.
19 . The semiconductor device of claim 17 further comprising a pixel electrode formed on said passivation layer.
20 . A method of manufacturing a semiconductor device, comprising the steps of:
providing a substrate; and forming a gate on said substrate; wherein nitrogen is provided when forming said gate, and the nitrogen flow rate is gradually adjusted from the beginning to the end of said gate formation.
21 . The method of claim 20 , wherein said substrate is a glass substrate.
22 . The method of claim 20 , wherein said nitrogen flow rate is gradually increasing so that the concentration of nitrogen in said gate increases from the near to the far of said substrate.
23 . The method of claim 20 , wherein said gate comprises a metal and nitrides of said metal.
24 . The method of claim 23 , wherein said metal is selected from the group consisting of Al, Cu, Ag, Mo, Cr, Ti, and their alloys, and AlNd.
25 . A method of manufacturing a semiconductor device, comprising the steps of:
providing a substrate; forming a gate on said substrate; forming a semiconductor layer on said gate; forming a source/drain on said substrate and simultaneously providing nitrogen whose flow rate is gradually adjusted from the beginning to the end of the formation of said source and said drain; and forming a channel between said source and said drain.
26 . The method of claim 25 , wherein said substrate is a glass substrate.
27 . The method of claim 25 , wherein the step of forming the gate is supplied with nitrogen whose flow rate is gradually adjusted from the beginning to the end of said gate formation.
28 . The method of claim 25 , wherein said nitrogen flow rate is gradually increasing so that the concentration of nitrogen in said gate increases from the near to the far of said substrate.
29 . The method of claim 25 , wherein said gate comprises a metal and nitrides of said metal.
30 . The method of claim 29 , wherein said metal is selected from the group of consisting of Al, Cu, Ag, Mo, Cr, Ti, and their alloys, and AlNd.
31 . The method of claim 25 , wherein said nitrogen flow rate first decreases then increases so that the concentration of nitrogen in said source/drain increases from the far and the near of said substrate.
32 . The method of claim 25 , wherein said source/drain comprises a metal and nitrides of said metal.
33 . The method of claim 32 , wherein said metal is selected from the group of consisting Al, Cu, Ag, Mo, Cr, Ti, and their alloys, and AlNd.
34 . The method of claim 25 further comprising the step of forming a gate insulating layer between said gate and said semiconductor layer.
35 . The method of claim 25 further comprising the step of forming an ohmic contact layer on said semiconductor layer.
36 . The method of claim 25 further comprising the step of forming a passivation layer on said substrate covering said gate, said semiconductor layer, and said source/drain.
37 . The method of claim 36 further comprising the step of forming a contact hole in said passivation layer.
38 . The method of claim 36 further comprising the step of forming a pixel electrode on said passivation layer.Cited by (0)
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