Parametric measuring circuit for minimizing oscillation effect

Abstract

A parametric measuring circuit for minimizing an oscillation effect is provided. The parametric measuring circuit comprises an input detection circuit, an oscillation effect eliminating logic circuit and an output selection circuit. The input detection circuit receives an input signal from an external input terminal and outputs the detection signal. The oscillation effect eliminating logic circuit is coupled to the input detection circuit for reducing/eliminating oscillation effect and outputting the detection signal. The output selection circuit is coupled to the oscillation effect eliminating logic circuit to select and transmit either the output signal generated from the internal circuit or the detection signal to the output terminal.

1 . A parametric measuring circuit for minimizing an oscillation effect, used to measure characteristics of plural input and output terminals of an integrated circuit, the parametric measuring circuit comprising: 
 an input detection circuit, coupled to the input terminals and receiving input signals therefrom to output a first detection signal;    an eliminating logic circuit, coupled to the input detection circuit and receiving the first detection signal to remove oscillation effect and output a second detection signal; and    an output selection circuit, coupled between an internal circuit and the output terminals of the integrated circuit, and coupled to the eliminating logic circuit, selecting and transmitting either the output signal from the internal circuit or the second detection signal to the output terminals.    
   
   
       2 . The parametric measuring circuit of  claim 1 , wherein the input detection circuit comprises a plurality of logic gates coupled to each other and to a last output terminal of a last-stage logic gate of the logic gates to output the first detection signal.  
   
   
       3 . The parametric measuring circuit of  claim 2 , wherein the logic gates are NAND gates.  
   
   
       4 . The parametric measuring circuit of  claim 2 , wherein the logic gates are NOR gates.  
   
   
       5 . The parametric measuring circuit of  claim 1 , wherein the eliminating logic circuit comprises a flip-flop coupled between the input detection circuit and the output selection circuit.  
   
   
       6 . The parametric measuring circuit of  claim 1 , wherein the output selection circuit comprises a plurality of multiplexers, each of the multiplexers is coupled between the internal circuit and one of the corresponding output terminals, and to the eliminating logic circuit, and each of the multiplexers selects and transmits either the output signal from the internal circuit or the second detection signal to one of the output terminals corresponding thereto.  
   
   
       7 . The parametric measuring circuit of  claim 6 , wherein the control circuit controls the output terminals to determine whether to enable the output terminals.