Method of forming storage node of capacitor in semiconductor memory, and structure therefor

Abstract

In one embodiment, an etch stop layer and a mold layer is sequentially formed on a semiconductor substrate having an interlayer insulation layer. The interlayer insulation layer includes a conductive region formed therein. The mold layer is partially etched to expose a top surface of the etching stop layer. The exposed etching stop layer and an upper portion of the interlayer insulating layer are removed to form a first aperture part that exposes a portion of the conductive region. The conductive region exposed in the first aperture part is etched to form a second aperture part. A conductive layer for the capacitor storage node is deposited on the semiconductor substrate having the first and second aperture parts. The conductive layer provided on the mold layer is planarized to form separated capacitor storage nodes.

1 . A semiconductor device comprising: 
 a transistor formed on a semiconductor substrate;    an interlayer insulating layer covering the transistor, the interlayer insulating layer having a contact pad electrically connected with an active region of the transistor; and    a capacitor storage node having a lower portion that is in contact with the contact pad, wherein the contact pad has a recessed portion adjacent an edge portion of an upper portion of the interlayer insulation layer.    
   
   
       2 . The device as claimed in  1 , wherein the contact pad is a capacitor storage node contact.