Thin film transistor

Abstract

A thin film transistor includes a substrate, a polysilicon layer, a patterned gate dielectric layer, a gate layer, a channel region, a source region, a drain region, and a LDD region. The polysilicon layer is positioned over the substrate. The patterned gate dielectric layer is positioned over the polysilicon layer. The patterned gate dielectric layer has a third and a fourth portion, wherein the fourth portion has a thickness smaller than that of the third portion. The gate layer is positioned over the third portion. The source region and the drain region are positioned in the polysilicon layer under the fourth portion. The channel region is positioned in the polysilicon layer under the gate layer. The LDD region is positioned in the polysilicon layer under the third portion and is between the channel region and the source region or between the channel region and the drain region.

1 . A thin film transistor, comprising: 
 a substrate;    a polysilicon layer disposed over said substrate;    a patterned gate dielectric layer disposed over the polysilicon layer, said patterned gate dielectric layer having a third portion and a fourth portion, wherein said fourth portion has a thickness smaller than that of said third portion;    a gate layer positioned over said third portion of said patterned gate dielectric layer;    a source region configured in said polysilicon layer under said fourth portion of said patterned gate dielectric layer;    a drain region configured in said polysilicon layer under said fourth portion of said patterned gate dielectric layer;    a channel region configured in said polysilicon layer under said gate layer; and    a lightly-doped-drain (LDD) region configured in said polysilicon layer under said third portion of said patterned gate dielectric layer, and between said channel region and said source region or between said channel region and said drain region.    
   
   
       2 . The transistor of  claim 1 , wherein said lightly-doped-drain (LDD) region is configured between said channel region and said source region and between said channel region and said drain region, and said lightly-doped-drain (LDD) region formed between said channel region and said source region has a same width as said lightly-doped-drain (LDD) region formed between said channel region and said drain region.  
   
   
       3 . The transistor of  claim 1 , wherein said lightly-doped-drain (LDD) region is positioned between said channel region and said source region and between said channel region and said drain region, and said lightly-doped-drain (LDD) region formed between said channel region and said source region has a width different from that of said lightly-doped-drain (LDD) region formed between said channel region and said drain region.  
   
   
       4 . The transistor of  claim 1 , further comprising: 
 a dielectric layer covering said gate layer and said patterned gate dielectric layer;    a source conductive layer positioned over said dielectric layer and passing through said dielectric layer and said patterned gate dielectric layer, said source conductive layer electrically connecting with said source region; and    a drain conductive layer positioned over said dielectric layer and passing through said dielectric layer and said patterned gate dielectric layer, said drain conductive layer electrically connecting with said drain region.    
   
   
       5 . The transistor of  claim 1 , further comprising a buffer layer positioned between said substrate and said polysilicon layer.