Method and structure in the manufacture of mask read only memory

Abstract

A method and structure of manufacture of mask ROM device is provided. Firstly, a semiconductor structure is provided that comprises a first dielectric layer, a plurality of buried bit lines and a plurality of code areas, wherein each of the code areas is placed between two buried bit lines. Next, a second dielectric layer having a plurality of contact plugs is formed on the semiconductor structure, wherein the contact plug comprises a second dielectric layer and a first glue layer, furthermore; the first glue layer is placed on the side-wall and bottom of the contact plugs. In addition, the contact plugs filled with the first metal layer. Then, a second glue layer, a second metal layer and a pad layer having an opening pattern are respectively formed on the second dielectric layer and contact plug. Thus, the processes of the present invention can improve the stability and accuracy in the electricity of the mask ROM device.

1 . A structure of mask read only memory, comprising: 
 a semiconductor structure having a first dielectric layer thereon, a plurality of buried bit lines and a plurality of code areas within said semiconductor structure, wherein each of said plurality of code areas is placed between two of plurality of said buried bit lines;    a second dielectric layer having a contact plug being placed on said semiconductor structure, wherein said contact plug comprises a first metal layer therein and a first glue layer thereon;    a second glue layer being on said second dielectric layer and said contact plug;    a second metal layer being on said second glue layer; and    a pad layer being on said second metal layer.    
   
   
       2 . The structure of mask read only memory according to  claim 1 , wherein said first dielectric layer is above said plurality of buried bit lines.  
   
   
       3 . The structure of mask read only memory according to  claim 1 , wherein said first metal layer is filled in said contact plug.  
   
   
       4 . The structure of mask read only memory according to  claim 1 , wherein the material of said first metal layer is tungsten.  
   
   
       5 . The structure of mask read only memory according to  claim 1 , wherein the material of said second dielectric layer is Borophosphosilicate Glass (BPSG).  
   
   
       6 . The structure of mask read only memory according to  claim 1 , wherein the material of said first glue layer is titanium/titanium nitride (Ti/TiN).  
   
   
       7 . The structure of mask read only memory according to  claim 1 , wherein said second glue layer comprises linear titanium/titanium nitride (Ti/TiN).