Simultaneous and selective partitioning of via structures using plating resist

Abstract

Systems and methods for simultaneously partitioning a plurality of via structures into electrically isolated portions by using plating resist within a PCB stackup are disclosed. Such via structures are made by selectively depositing plating resist in one or more locations in a sub-composite structure. A plurality of sub-composite structures with plating resist deposited in varying locations are laminated to form a PCB stackup of a desired PCB design. Through-holes are drilled through the PCB stackup through conductive layers, dielelectric layers and through the plating resist. Thus, the PCB panel has multiple through-holes that can then be plated simultaneously by placing the PCB panel into a seed bath, followed by immersion in an electroless copper bath. Such partitioned vias increase wiring density and limit stub formation in via structures. Such partitioned vias allow a plurality of electrical signals to traverse each electrically isolated portion without interference from each other.

1 . A multilayer PCB, said multilayer PCB comprising: 
 at least one sub-composite structure having a dielectric layer sandwiched between a first conductive layer and a second conductive layer;    wherein said first conductive layer includes a clearance filled with plating resist; and    a through-hole drilled through said multilayer PCB and passing through said plating resist, wherein an interior surface of said through-hole is plated with conductive material in areas of said interior surface that are devoid of said plating resist to form a partitioned via structure through said multilayer PCB.    
   
   
       2 . A sub-composite structure for use with a multilayer PCB, said sub-composite structure comprising: 
 a dielectric layer sandwiched between two conductive layers; and    wherein one conductive layer of said two conductive layers includes a clearance filled with plating resist.    
   
   
       3 . A multilayer PCB, said multilayer PCB comprising: 
 at least one sub-composite structure having: 
 a dielectric layer sandwiched between a first conductive layer and a second conductive layer; and  
 a first through-hole drilled through said at least one sub-composite structure passing through first conductive layer, said dielectric layer and said second conductive layer, wherein said first through-hole being filled with plating resist;  
   a second through-hole drilled through said multilayer PCB and passing through said plating resist, wherein an interior surface of said second through-hole is plated with conductive material in areas that are devoid of said plating resist to form a partitioned via structure through said multilayer PCB.    
   
   
       4 . A sub-composite structure for use with a multilayer PCB, said sub-composite structure comprising: 
 a dielectric layer sandwiched between a first conductive layer and a second conductive layer; and    a through-hole drilled through said sub-composite structure passing through said first conductive layer, said dielectric layer and said second conductive layer, wherein said through-hole is filled with plating resist.    
   
   
       5 . A multilayer PCB, said multilayer PCB comprising: 
 at least one sub-composite structure having: 
 a dielectric layer sandwiched between a first conductive layer and a second conductive layer; and  
 a blind-hole drilled through said first conductive layer and said dielectric layer, wherein said blind-hole being filled with plating resist;  
   a through-hole drilled through said multilayer PCB and passing through said plating resist, wherein an interior surface of said through-hole is plated with conductive material in areas that are devoid of said plating resist to form a partitioned via structure through said multilayer PCB.    
   
   
       6 . A sub-composite structure for use with a multilayer PCB, said sub-composite structure comprising: 
 a dielectric layer sandwiched between a first conductive layer and a second conductive layer; and    a blind-hole drilled through said first conductive layer and said dielectric layer, wherein said blind-hole being filled with plating resist.    
   
   
       7 . A multilayer PCB, said multilayer PCB comprising: 
 at least one sub-composite structure having: 
 a dielectric layer sandwiched between a first conductive layer and a second conductive layer, wherein said first conductive layer includes region that exposes a portion of said dielectric layer; and  
 a selective deposit of plating resist deposited on said exposed dielectric;  
   a through-hole drilled through said multilayer PCB and passing through said layer of plating resist, wherein an interior surface of said through-hole is plated with conductive material in areas that are devoid of said plating resist to form a partitioned via structure through said multilayer PCB.    
   
   
       8 . A sub-composite structure for use with a multilayer PCB, said sub-composite structure comprising: 
 a dielectric layer sandwiched between a first conductive layer and a second conductive layer, wherein said first conductive layer includes region that exposes a portion of said dielectric layer; and    a selective deposit of plating resist deposited on said exposed dielectric.    
   
   
       9 . A multilayer PCB, said multilayer PCB comprising: 
 at least one sub-composite structure having: 
 a dielectric layer sandwiched between a conductive pad and a conductive layer; and  
 a selective deposit of plating resist deposited on said conductive pad;  
   a through-hole drilled through said multilayer PCB and passing through said layer of plating resist, wherein an interior surface of said through-hole is plated with conductive material in areas that are devoid of said plating resist to form a partitioned via structure through said multilayer PCB.    
   
   
       10 . A sub-composite structure for use with a multilayer PCB, said sub-composite structure comprising: 
 a dielectric layer sandwiched between a conductive pad and a conductive layer, and    a selective deposit of plating resist deposited on said conductive pad.    
   
   
       11 . A method of partitioning via structures, the method comprising: 
 forming at least one clearance within one or more of a first conductive layer, a dielectric layer, and a second conductive layer of at least one sub-composite structure; and    depositing plating resist in said at least one clearance.    
   
   
       12 . The method of  claim 11 , further comprising: 
 laminating said at least one sub-composite structure to a multilayer PCB stackup;    drilling a through-hole through said multilayer PCB stackup passing through each area of said plating resist; and    processing said PCB stackup for plating an interior surface of each through-hole with a conductive material in areas that are devoid of said plating resist to form corresponding partitioned via structures through said multilayer PCB.    
   
   
       13 . The method of  claim 12 , wherein said plating comprises using an electrolytic plating operation.  
   
   
       14 . The method of  claim 12 , wherein said plating comprises using an electroless plating operation.  
   
   
       15 . The method of  claim 11 , wherein said plating resist comprises an insulating hydrophobic resinous material that is resistant to a deposition of a catalytic species capable of catalyzing an electroless metal deposition.  
   
   
       16 . The method of  claim 15 , wherein said insulating hydrophobic resinous material include one or more of: silicone resins, polyethylene resins, fluorocarbon resins, polyurethane resins, and acrylic resins.  
   
   
       17 . The method of  claim 15 , wherein said insulating hydrophobic resinous material is used alone or in a combined composition with other resinous materials in amounts sufficient to maintain hydrophobic properties in said combined composition.  
   
   
       18 . The method of  claim 11 , wherein said plating resist is a dry film.  
   
   
       19 . The method of  claim 11 , wherein said plating resist comprises a paste or viscous liquid.  
   
   
       20 . The method of  claim 12 , where said partitioned via structure is filled with any one of an electrically insulating, ohmically resistive paste and voltage switchable dielectric material to improve reliability or functionality.  
   
   
       21 . The method of  claim 12 , where the insulating dielectric material is one or more of: FR4, epoxy glass, polyimide glass, ceramic hydrocarbon, polyimide film, resin impregnated woven glass, Teflon film, resin impregnated matte material, Kevlar, paper, resin dielectrics with dispersed nano-powders.  
   
   
       22 . The method of  claim 11 , further comprising using a computer program to determine locations for selectively depositing said plating resist, and for generating information for use by one or more of a PCB design layout program and a computer aided manufacturing system for selectively depositing said plating resist and for routing circuit traces through said partitioned via structures.  
   
   
       23 . The method of  claim 11 , further comprising depositing said plating resist at locations for backdrilling in pre-existing PCB designs that include backdrilling of via structures.  
   
   
       24 . The method of  claim 11 , further comprising depositing said plating resist at locations separating two or more separate PCB subassemblies during sequential processing.