Scalable rundown protection for object lifetime management

Abstract

A system and method for object rundown protection that scales with the number of processors in a shared-memory computer system is disclosed. In an embodiment of the present invention, prior to object rundown, a cache-aware reference count data structure is used to prevent cache-pinging that would otherwise result from data sharing across processors in a multiprocessor computer system. In this data structure, a counter of positive references and negative dereferences, aligned on a particular cache line, is maintained for each processor. When an object is to be destroyed, a rundown wait process is begun, during which new references on the object are prohibited, and the total number of outstanding references is added to an on-stack global counter. Destruction is delayed until the global reference count is reduced to zero. In an embodiment of the invention suited to implementation on non-uniform memory access multiprocessor machines, each processor's reference count is additionally allocated in a region of main memory that is physically close to that processor.

1 . A computer system comprising: 
 a plurality of processors;    a memory hierarchy including a main memory shared by the processors and at least one faster-access memory level comprising a plurality of units, each associated with one of the processors; and    routines for preventing a shared object from being destroyed or otherwise rendered inaccessible while at least one reference on the object exists, the routines including a plurality of per-processor reference counts, maintained in the units of the memory.    
   
   
       2 . The computer system of  claim 1  wherein the at least one faster-access memory level includes a level of local cache memory units, wherein each local cache unit is private to the respective processor associated with the cache unit.  
   
   
       3 . The computer system of  claim 1  wherein the computer system is a non-uniform memory access (NUMA) multiprocessor machine, and the at least one faster-access memory level includes a level comprising subsets of the main memory, wherein each subset is physically close to the processor with which it is associated.