Semiconductor device and method of fabricating the same

Abstract

A semiconductor device includes a semiconductor substrate, a gate insulating film formed on the semiconductor substrate, a gate electrode formed on the gate insulating film, a source/drain diffusion layer formed in the semiconductor substrate at both sides of the gate electrode, and a channel region formed in the semiconductor substrate between a source and a drain of the source/drain diffusion layer and arranged below the gate insulating film, wherein an upper surface of the source/drain diffusion layer is positioned below a bottom surface of the gate electrode, and an upper surface of the channel region is positioned below the upper surface of the source/drain diffusion layer.

1 . A semiconductor device comprising: 
 a semiconductor substrate;    a gate insulating film formed on the semiconductor substrate;    a gate electrode formed on the gate insulating film;    a source/drain diffusion layer formed in the semiconductor substrate at both sides of the gate electrode; and    a channel region formed in the semiconductor substrate between a source and a drain of the source/drain diffusion layer and arranged below the gate insulating film,    wherein an upper surface of the source/drain diffusion layer is positioned below a bottom surface of the gate electrode, and an upper surface of the channel region is positioned below the upper surface of the source/drain diffusion layer.    
   
   
       2 . The device according to  claim 1 , wherein a film thickness of the gate insulating film increases from a center of the channel region toward the source/drain diffusion layer.  
   
   
       3 . The device according to  claim 1 , further comprising a nitrogen-containing insulating film formed on the source/drain diffusion layer.  
   
   
       4 . The device according to  claim 3 , wherein a nitrogen concentration in a first end portion of the nitrogen-containing insulating film, which is adjacent to the gate electrode is lower than a nitrogen concentration in a second end portion of the nitrogen-containing insulating film, which is opposite to the first end portion of the nitrogen-containing insulating film.  
   
   
       5 . The device according to  claim 3 , wherein an upper surface of the nitrogen-containing insulating film is positioned below the bottom surface of the gate electrode.  
   
   
       6 . The device according to  claim 1 , further comprising a gate sidewall oxide film which is formed on a side surface of the gate electrode, and thins from the bottom surface to an upper surface of the gate electrode.  
   
   
       7 . The device according to  claim 1 , further comprising an interface nitride layer formed in a first interface between the gate electrode and gate insulating film, and in a second interface between the gate insulating film and semiconductor substrate.  
   
   
       8 . The device according to  claim 1 , in which the gate electrode is a floating gate electrode of a nonvolatile memory cell transistor, and the gate insulating film is a tunnel insulating film, and 
 which further comprises:    an inter-electrode insulating film formed on the gate electrode; and    a control gate electrode formed on the inter-electrode insulating film.    
   
   
       9 . The device according to  claim 8 , further comprising a nitrogen-containing insulating film formed on the source/drain diffusion layer.  
   
   
       10 . The device according to  claim 9 , wherein a nitrogen concentration in an end portion of the nitrogen-containing insulating film is lower than a nitrogen concentration in a central portion of the nitrogen-containing insulating film.  
   
   
       11 . A semiconductor device manufacturing method comprising: 
 forming a gate insulating film on a semiconductor substrate;    selectively forming a gate electrode on the gate insulating film;    forming a nitrogen-containing insulating film by nitriding an exposed portion of the gate insulating film;    performing thermal oxidation that an oxide amount at an upper surface of the semiconductor substrate and at a bottom surface of the gate electrode reduces from an end portion to a central portion of a channel region beneath the gate electrode, forming a sidewall layer on a side surface of the gate electrode, and thickening the gate insulating film in a lower end portion of the gate electrode; and    forming a source/drain diffusion layer in the semiconductor substrate.    
   
   
       12 . The method according to  claim 11 , wherein an upper surface of the source/drain diffusion layer is positioned below a bottom surface of the gate electrode, and an upper surface of the channel region is positioned below the upper surface of the source/drain diffusion layer.  
   
   
       13 . The method according to  claim 11 , wherein the nitrogen-containing insulating film is formed that a nitrogen concentration in a first end portion of the nitrogen-containing insulating film, which is adjacent to the gate electrode is lower than a nitrogen concentration in a second end portion of the nitrogen-containing insulating film, which is opposite to the first end portion of the nitrogen-containing insulating film.  
   
   
       14 . The method according to  claim 11 , further comprising forming a gap between the nitrogen-containing insulating film and an end portion of the gate electrode.  
   
   
       15 . The method according to  claim 11 , further comprising forming an interface nitride layer in a first interface between the gate electrode and gate insulating film, and in a second interface between the gate insulating film and semiconductor substrate.  
   
   
       16 . The method according to  claim 11 , wherein the thermal oxidation increases a film thickness of the gate insulating film from a center of the channel region toward the source/drain diffusion layer.  
   
   
       17 . The method according to  claim 11 , wherein a film thickness of the sidewall layer decreases from the bottom surface to an upper surface of the gate electrode.  
   
   
       18 . The method according to  claim 11 , further comprising removing the gate insulating film below an end portion of the gate electrode, after the nitrogen-containing insulating film is formed and before the thermal oxidation is performed.  
   
   
       19 . The method according to  claim 11 , in which the gate electrode is a floating gate electrode of a nonvolatile memory cell transistor, and the gate insulating film is a tunnel insulating film, and 
 which further comprises:    forming an inter-electrode insulating film on the gate electrode; and    forming a control gate electrode on the inter-electrode insulating film.    
   
   
       20 . The method according to  claim 19 , wherein an upper surface of the source/drain diffusion layer is positioned below a bottom surface of the gate electrode, and an upper surface of the channel region is positioned below the upper surface of the source/drain diffusion layer.