Programmable element latch circuit

Abstract

An antifuse latch device and method for performing a redundancy pretest without the use of additional test circuitry is disclosed. Conventional antifuse latch devices are designed such that a redundancy pretest cannot be performed on the antifuse latch device once the antifuses are programmed but rather requires additional circuitry to map the appropriate address bits to test the redundant row or column. The present invention adds a level translating inverter to a conventional antifuse latch device, thus allowing the antifuse latch device to simulate an unblown antifuse by isolating the antifuse from the latch.

1 - 42 . (canceled)  
   
   
       43 . A method of testing an electrical device comprising: 
 programming a fusible device into a programmed state during a first-time interval;    receiving a signal corresponding to said programmed state at a first input of a latch circuit during a second time interval;    receiving a control signal at a second input of said latch circuit, said control signal having a first state during a third time interval and a second state during a fourth time interval; and    producing an output signal at an output of said latch circuit, said output signal having a state dependent on said programmed state during said third time interval, and said output signal having a state independent of said programmed state during said fourth time interval.    
   
   
       44 . A method of testing an electrical device as defined in  claim 43  wherein said second time interval encompasses said third and fourth time intervals.  
   
   
       45 . A method of testing an electrical device as defined in  claim 43  wherein said fusible device comprises an antifuse device.  
   
   
       46 . A method of testing an electrical device as defined in  claim 43  wherein said programming said fusible device into a programmed state comprises applying a programming voltage to said fusible device.  
   
   
       47 . A programmable device comprising: 
 fusible means for storing a data state;    circuit means for reading said data state and producing a data output dependent on said data state during a first time interval;    said circuit means being adapted to produce a data output independent of said data state during a second time interval, said second time interval being subsequent to said first time interval.    
   
   
       48 . A programmable device as defined in  claim 47 , wherein said circuit means for reading said data state comprises an inverter circuit.  
   
   
       49 . A programmable device as defined in  claim 48  wherein said inverter circuit comprises a level translating inverter.  
   
   
       50 . A programmable device as defined in  claim 47  further comprising a signal input adapted to receive a control signal, said control signal having a first state corresponding to said first time interval and a second state corresponding to said second time interval.  
   
   
       51 . A programmable device as defined in  claim 47  wherein said fusible means comprises an antifuse.  
   
   
       52 . A programmable device as defined in  claim 47  wherein said fusible means comprises a flash memory cell.