Memory cell arrays

Abstract

A memory device includes memory cells, bit lines, active areas, and transistors formed in each active area and electrically coupling memory cells to corresponding bit lines. The memory cells can have an area of about 6F 2 , and the bit lines can be coupled to sense amplifiers in a folded bit line configuration. Each bit line may include a first level portion and a second level portion.

1 . A memory device, comprising: 
 memory cells each having an area of about 6F 2 ;    sense amplifiers;    bit lines coupled to the sense amplifiers in a folded bit line configuration, each bit line including a first level portion and a second level portion; and    active areas, transistors being formed in the active areas and electrically coupling corresponding memory cells to corresponding first level bit lines.    
   
   
       2 . The memory device of  claim 1 , wherein each pair of bit lines is vertically twisted at one or more predetermined locations, the bit lines in the pair transitioning between the first level portion and the second level portion at each twist.  
   
   
       3 . The memory device of  claim 2 , wherein a column pitch of each memory cell is 2F.  
   
   
       4 . The memory device of  claim 1 , wherein each memory cell includes a capacitor formed over the first level portion of each bit line.  
   
   
       5 . The memory device of  claim 4 , wherein the second level portion of each bit line is formed over each capacitor.  
   
   
       6 . The memory device of  claim 1 , wherein the bit lines extend generally along the same direction as the active areas, the bit lines intersecting the active areas at slanted portions, 
 the semiconductor device further comprising contacts between the bit lines and active areas formed in the slanted portions.    
   
   
       7 . The memory device of  claim 6 , wherein the active areas are generally straight and the bit lines extend in a wavy pattern.  
   
   
       8 . The memory device of  claim 6 , wherein the bit lines are generally straight and the active areas extend in a wavy pattern.  
   
   
       9 . The memory device of  claim 6 , each bit line having a first portion on a first side of a corresponding active area, a second portion on a second side of the corresponding active area, and a third portion on the first side of the active area.  
   
   
       10 . The memory device of  claim 6 , wherein the bit lines extend along generally the same direction as the active areas so that the bit lines and active areas intersect at predetermined locations.  
   
   
       11 . A method of making a memory device, comprising: 
 forming memory cells each having an area of about 6F 2 ;    forming sense amplifiers;    coupling bit lines to the sense amplifiers in a folded bit line arrangement;    forming transistors in active areas; and    the transistors electrically coupling corresponding memory cells to corresponding bit lines.    
   
   
       12 . The method of  claim 11 , further comprising: 
 forming each bit line of a first level portion and a second level portion; and    coupling each transistor to the first level portion of the corresponding bit line.    
   
   
       13 . The method of  claim 12 , further comprising: 
 vertically twisting each pair of bit lines at one or more predetermined locations; and    transitioning the bit lines in the pair between the first level portion and the second level portion at each twist.    
   
   
       14 . The method of  claim 13 , further comprising forming a capacitor of each memory cell over the first level portion of each bit line.  
   
   
       15 . The method of  claim 14 , further comprising forming the second level portion of each bit line over the capacitor.  
   
   
       16 . The method of  claim 11 , wherein coupling the bit lines to the sense amplifiers in the folded bit line arrangement comprises coupling each pair of bit lines to a same side of each corresponding sense amplifier.