Fabrication of lean-free stacked capacitors

Abstract

For fabricating lean-free stacked capacitors, openings are formed through layers of materials including a layer of support material displaced from a bottom of the openings. A respective first electrode is formed for a respective capacitor within each of the openings. The layer of support material is patterned to form support structures around the first electrodes. Masking spacers are formed around exposed top portions of the first electrodes, and exposed portions of the support material are etched away to form the support structures. Such stacked capacitors are applied within a DRAM (dynamic random access memory).

1 . An array of capacitors, comprising: 
 a plurality of stacked capacitors each respectively having a first electrode; and    a plurality of support structures including a respective disc surrounding each first electrode and including joining portions that are disposed between the first electrodes of adjacent capacitors.    
     
     
         2 . The array of capacitors of  claim 1 , further comprising: 
 a respective masking spacer disposed on each disc and a respective mask structure disposed on each joining portion.    
     
     
         3 . The array of capacitors of  claim 1 , further including: 
 a layer of mount material surrounding the first electrodes toward the bottom of the first electrodes.    
     
     
         4 . The array of capacitors of  claim 3 , wherein the support structures are disposed between the mount material and the top of the first electrode.  
     
     
         5 . The array of capacitors of  claim 4 , wherein the mount material and the support structures are comprised of silicon nitride.  
     
     
         6 . The array of capacitors of  claim 1 , wherein the support structures are comprised of silicon nitride.  
     
     
         7 . The array of capacitors of  claim 1 , wherein the respective disc surrounding each first electrode is a circular disc.  
     
     
         8 . The array of capacitors of  claim 1 , wherein each of the capacitors is formed onto a respective conductive plug coupled to a junction of a respective switching transistor.  
     
     
         9 . The array of capacitors of  claim 8 , wherein the array of capacitors is formed as part of a DRAM (dynamic random access memory).  
     
     
         10 . The array of capacitors of  claim 9 , wherein the first electrode is a storage node for each capacitor.