Semiconductor processing methods of forming integrated circuitry

Abstract

Semiconductor processing methods of forming integrated circuitry are described. In one embodiment, memory circuitry and peripheral circuitry are formed over a substrate. The peripheral circuitry comprises first and second type MOS transistors. Second type halo implants are conducted into the first type MOS transistors in less than all of the peripheral MOS transistors of the first type. In another embodiment, a plurality of n-type transistor devices are formed over a substrate and comprise memory array circuitry and peripheral circuitry. At least some of the individual peripheral circuitry n-type transistor devices are partially masked, and a halo implant is conducted for unmasked portions of the partially masked peripheral circuitry n-type transistor devices. In yet another embodiment, at least a portion of only one of the source and drain regions is masked, and at least a portion of the other of the source and drains regions is exposed for at least some of the peripheral circuitry n-type transistor devices. A halo implant is conducted relative to the exposed portions of the source and drain regions. In another embodiment, a common masking step is used and a halo implant is conducted of devices formed over a substrate comprising memory circuitry and peripheral circuitry sufficient to impart to at least three of the devices three different respective threshold voltages.

1 - 49 . (canceled)  
   
   
       50 . A semiconductor processing method comprising: 
 a masking step providing a common mask; and    an implant step carried out through the common mask, comprising conducting a halo implant of devices formed over a substrate comprising memory circuitry and peripheral circuitry sufficient to impart to at least three of the devices three different respective threshold voltages, at least some of the devices forming memory access devices.    
   
   
       51 . The method of  claim 50 , wherein the at least some of the devices forming memory access devices receive halo implants on a bit line contact side of the devices.  
   
   
       52 . A method of improving DRAM storage cell retention time comprising conducting, in a common masking step and in a common implant step, a halo implant of devices formed over a substrate comprising memory circuitry and peripheral circuitry sufficient to impart to each device one of two or more different respective threshold voltages, at least some of the devices forming memory access devices, wherein the at least some of the devices forming memory access devices receive halo implants on a bit line contact side of the devices.  
   
   
       53 . The method of  claim 52  wherein the halo implant is performed prior to formation of sidewall spacers in the memory access devices.  
   
   
       54 . The method of  claim 52  wherein the halo implant is performed after formation of sidewall spacers in the memory access devices.  
   
   
       55 . The method of  claim 52  wherein the halo implant is accompanied with an n-minus implant on the bit line contact side.  
   
   
       56 . The method of  claim 52  wherein the storage node side of the memory access device is masked from the halo implant.  
   
   
       57 . A method of improving DRAM storage cell retention time comprising forming memory access devices having different implants and hence different junction structures on a bit line contact side and a storage node side respectively.  
   
   
       58 . The method of  claim 57  wherein forming memory access devices includes: 
 performing, during a masking and implant step, a one-sided halo implant on the bit line contact side; and    performing, during the masking and implant step, an n-minus implant on the bit line contact side.    
   
   
       59 . The method of  claim 58 , wherein performing a one-sided halo implant is performed prior to formation of sidewall spacers.  
   
   
       60 . The method of  claim 57 , wherein the storage node side is masked during a one-sided halo implant on the bit line contact side.