Exponent encoder circuit and mask circuit

Abstract

In order to provide an exponent encoder circuit for obtaining an exponent constituted by a left shift amount for normalizing input data with code bits, there is provided a first logic circuit for inverting data portions other than code bits and shifting the code bits to least significant bit positions when inputted data is a negative number and allowing data portions other than the code bits to pass as is and moving the code bits to least significant bit positions when the inputted data is a positive number, and a second logic circuit for putting a plurality of logic operation equations for obtaining each bit of an exponent from output of the first logic circuit as decided by a truth table for outputs of the first logic circuit and corresponding exponents in a form where common terms are cancelled out.

1 . A mask circuit having n-bit input data where the most significant bit of bit positions at one level is a marker logic level bit, with all bits at bit positions of lower significance than the marker logic level bit being put at one logic level and all bits at bit positions of greater significance than the bit position of the marker logic level bit being put at another logic level, said circuit comprising: 
 output data lines of the same number as there are items of input data;    output line initialization transistors for charging (or discharging) each output line and putting each output line to a logic level based on an output line pre-processing signal;    n output fixing transistors provided for n (where n=1 to N) output lines, for discharging (or charging) the respective output lines by inputting marker logic level bits to respective gates; and    input lines for inputting n bit values from the most significant bit side of the input data to respective gates of the n output fixing transistors for the nth (where n=1 to N) output line,    wherein the input data is inputted to each input line after all of the output lines are put to one logic level based on the pre-processing signal for the output lines so that output data is formed at each of the output lines.    
   
   
       2 . The mask circuit of  claim 1 , wherein each of the output line initialization transistors are transistors of a first conductive type with sources connected to power supply potential, gates connected to the output line pre-processing signal and drains connected to each of the output lines respectively, and each of the output fixing transistors are transistors of a second conductive type with sources connected to earth potential, gates connected to the input lines, and drains connected to each of the output lines, respectively.  
   
   
       3 . The mask circuit of  claim 2 , wherein the transistor of the first conductive type is a PMOS type transistor and the transistor of the second conductive type is an NMOS type transistor.  
   
   
       4 . The mask circuit of  claim 2 , wherein the transistor of the first conductive type is a NMOS type transistor and the transistor of the second conductive type is an PMOS type transistor.  
   
   
       5 . An exponent encoder circuit for obtaining an exponent constituted by a left shift amount for normalizing input data with code configured with a two bit exponent, said circuit comprising: 
 a code matching circuit for converting to data for a positive number so that exponents become the same when inputted data is a negative number (or a positive number) and allowing data to pass as is when the inputted data is a positive number (or negative number);    a mask circuit where a most significant bit position is included giving a marker logic level bit within the output of the code matching circuit with all bits at bit positions of lower significance being put at one logic level and all bits at bit positions of greater significance than the bit position of the most significant bit position given by the marker logic level bit being put at another logic level; and    an encoder circuit for generating an exponent from the output of the mask circuit.    
   
   
       6 . The exponent encoder circuit of  claim 5 , wherein that disclosed in  claim 3  is used as the mask circuit.  
   
   
       7 . The exponent encoder circuit of  claim 5 , wherein a parallel shift configuration circuit is used as the mask circuit.  
   
   
       8 . The exponent encoder circuit of  claim 5 , wherein the encoder circuit comprises exclusive OR circuits inputted with data where more significant side bits have one logical level and less significant side bits have another logic level, for detecting a boundary of bits of the one logic level and bits of the other logic level, and an exponent generating circuit for decoding boundary detection results at the output of the exclusive OR circuit.