Circuits and methods for interconnecting bus systems

Abstract

Circuits and methods for interconnecting a live backplane and at least one I/O card are provided. This invention provides interconnection circuitry that utilizes buffer circuitry to connect the data and clock busses of the backplane to the data and clock busses of the I/O card in a “hot-swappable” fashion. Buffer circuitry also isolates the capacitance associated with the backplane from the capacitance associated with the I/O card. For example, when at least one signal is driven from the backplane to the I/O card, the signal need only overcome the capacitance associate with the backplane. Conversely, when at least one signal is driven from the I/O card to the backplane, the signal need only overcome the capacitance associated with the I/O card. Hence, this capacitive isolation facilitates signal propagation between the backplane and the I/O card.

1 - 47 . (canceled)  
     
     
         48 . A method for interconnecting a live backplane having a data bus and a clock bus to at least a first I/O card having a data bus and a clock bus, said method comprising: 
 assigning a digital interconnection address to interconnection circuitry associated with said first I/O card; and    addressing the digital interconnection address assigned to said interconnection circuitry when it is suitable to couple said backplane and said first I/O card data busses together and to couple said backplane and first I/O card clock busses together.    
     
     
         49 . The method of  claim 48  further comprising: 
 instructing said backplane and first I/O card data busses to couple together and said backplane and first I/O card clock busses to couple together after said interconnection circuitry has been addressed.    
     
     
         50 . The method of  claim 49  further comprising: 
 prior to said instructing, charging said backplane and said first I/O card data and clock busses to a predetermined voltage level; and    ceasing said charging when said backplane and first I/O card data and clock busses are coupled together.    
     
     
         51 . The method of  claim 48 , wherein said addressing comprises: 
 sending data signals over said backplane data bus in conjunction with clock signals provided by said backplane clock bus to address said interconnection circuitry.    
     
     
         52 . The method of  claim 49 , wherein said instructing comprises: 
 sending data signals over said backplane data bus in conjunction with clock signals provided by said backplane clock bus to instruct said interconnection circuitry.    
     
     
         53 - 59 . (canceled)  
     
     
         60 . The method of  claim 48  further comprising: 
 determining a suitable condition to couple said backplane and said first I/O card data busses together and to couple said backplane and first I/O card clock busses together.    
     
     
         61 . The method of  claim 60  wherein said determining said suitable condition comprises: 
 monitoring the backplane and said first I/O card data and clock busses to determine a condition.    
     
     
         62 . The method of  claim 61  wherein said condition is reaching a predetermined voltage level.  
     
     
         63 . The method of  claim 48  further comprising: 
 performing a connection sequence to couple said backplane and said first I/O card data busses together and to couple said backplane and first I/O card clock busses together when said interconnection circuitry is addressed.    
     
     
         64 . The method of  claim 48  further comprising: 
 coupling said backplane and said first I/O card data and clock busses together when it is suitable.