Semiconductor devices having a hybrid channel layer, current aperture transistors and methods of fabricating same

Abstract

Transistors and/or methods of fabricating transistors that include a source contact, drain contact and gate contact are provided. In some embodiments, a channel region is provided between the source and drain contacts and at least a portion of the channel regions includes a hybrid layer comprising semiconductor material. In particular embodiments of the present invention, the transistor is a current aperture transistor. The channel region may include pendeo-epitaxial layers or epitaxial laterally overgrown layers. Transistors and methods of fabricating current aperture transistors that include a trench that extends through the channel and barrier layers and includes semiconductor material therein are also provided.

1 . A transistor comprising: 
 a mask region on a substrate;    a first epitaxial laterally overgrown layer comprising semiconductor material of a first conductivity type on the substrate and at least a portion of the mask region;    a second epitaxial laterally overgrown layer comprising semiconductor material of a second conductivity type and/or insulating on the first epitaxial laterally overgrown layer comprising semiconductor material and at least a portion of the mask region and that includes spaced apart portions that extend from end surfaces of the portions of the first epitaxial laterally overgrown layer on the mask region that are the first conductivity type;    a third epitaxial laterally overgrown layer comprising unintentionally doped semiconductor material on the second epitaxial laterally overgrown layer and that includes portions that extend from the spaced apart portions and coalesce and are the first conductivity type;    a channel layer comprising semiconductor material on the third epitaxial laterally overgrown layer;    a barrier layer on the channel layer;    a source contact on the barrier layer;    a gate contact on the barrier layer; and    a drain contact electrically connected to the first layer comprising semiconductor material.    
   
   
       2 . The transistor of  claim 1 , further comprising a first layer comprising semiconductor material comprising the first conductivity type on the substrate and wherein the mask region is on the first layer and the first epitaxial laterally overgrown layer is provided on the first layer.  
   
   
       3 . The transistor of  claim 1 , wherein the first conductivity type is n-type and the second conductivity type is p-type.  
   
   
       4 . The transistor of  claim 1 , wherein the semiconductor material comprises a nitride-based semiconductor material.  
   
   
       5 . The transistor of  claim 4 , wherein the substrate comprises gallium nitride.  
   
   
       6 . The transistor of  claim 4 , wherein the substrate comprises silicon carbide.  
   
   
       7 . The transistor of  claim 6 , wherein the silicon carbide substrate is the first conductivity type and wherein the drain contact is provided on the silicon carbide substrate.  
   
   
       8 . The transistor of  claim 4 , wherein the nitride-based semiconductor material comprises a GaN based semiconductor material.  
   
   
       9 . A current aperture transistor comprising: 
 a first layer comprising semiconductor material of a second conductivity type or insulating on a substrate;    a channel layer comprising semiconductor material on the second layer;    a barrier layer on the channel layer;    a trench extending through the barrier layer, the channel layer and the first layer, the trench including semiconductor material of a first conductivity type therein;    a gate contact on the barrier layer;    a source contact on the barrier layer and opposite the trench from the gate contact; and    a drain contact electrically connected to the first layer.    
   
   
       10 . The transistor of  claim 9 , further comprising a second layer comprising semiconductor material of the first conductivity type on the substrate between the substrate and the first layer; and wherein the trench extends to the second layer.  
   
   
       11 . The transistor of  claim 9 , wherein the first conductivity type is n-type and the second conductivity type is p-type.  
   
   
       12 . The transistor of  claim 9 , wherein the semiconductor material comprises a nitride-based semiconductor material.  
   
   
       13 . The transistor of  claim 12 , wherein the substrate comprises gallium nitride.  
   
   
       14 . The transistor of  claim 12 , wherein the substrate comprises silicon carbide.  
   
   
       15 . The transistor of  claim 14 , wherein the silicon carbide substrate is the first conductivity type and wherein the drain contact is provided on the silicon carbide substrate.  
   
   
       16 . The transistor of  claim 9 , wherein the nitride-based semiconductor material comprises a GaN based semiconductor material.  
   
   
       17 . The transistor of  claim 9 , further comprising an insulating layer between the gate contact and the barrier layer.  
   
   
       18 . The transistor of  claim 9 , further comprising contact regions of semiconductor material of the first conductivity type between the source contact and the barrier layer.  
   
   
       19 . The transistor of  claim 10 , wherein the trench extends into the first layer.  
   
   
       20 . The transistor of  claim 10 , further comprising a third layer comprising semiconductor material of the first conductivity type disposed between the substrate and the second layer comprising semiconductor material.  
   
   
       21 . A method of fabricating a transistor comprising: 
 forming a mask region on a substrate;    forming a first epitaxial laterally overgrown layer comprising semiconductor material of a first conductivity type by epitaxial lateral overgrowth on the first layer comprising semiconductor material and at least a portion of the mask region;    forming a second epitaxial laterally overgrown layer comprising semiconductor material of a second conductivity type and/or insulating by epitaxial lateral overgrowth on the first epitaxial laterally overgrown layer comprising semiconductor material and at least a portion of the mask region and that includes spaced apart portions that extend from end surfaces of the portions of the first epitaxial laterally overgrown layer on the mask region that are the first conductivity type;    forming a third epitaxial laterally overgrown layer comprising unintentionally doped semiconductor material by epitaxial lateral overgrowth on the second epitaxial laterally overgrown layer and that includes portions that extend from the spaced apart portions and coalesce and are the first conductivity type;    forming a channel layer comprising semiconductor material on the third epitaxial laterally overgrown layer;    forming a barrier layer on the channel layer;    forming a source contact on the barrier layer;    forming a gate contact on the barrier layer; and    forming a drain contact electrically connected to the first layer comprising semiconductor material.    
   
   
       22 . The method of  claim 21 , further comprising forming a first layer comprising semiconductor material of a first conductivity type on the substrate, wherein forming a mask region comprises forming a mask region on the first layer and wherein forming a first epitaxial laterally overgrown layer comprises forming a first epitaxial laterally overgrown layer on the first layer.  
   
   
       23 . The method of  claim 21 , wherein the first conductivity type is n-type and the second conductivity type is p-type.  
   
   
       24 . The method of  claim 21 , wherein the semiconductor material comprises a nitride-based semiconductor material.  
   
   
       25 . The method of  claim 24 , wherein the substrate comprises gallium nitride.  
   
   
       26 . The method of  claim 24 , wherein the substrate comprises silicon carbide.  
   
   
       27 . The method of  claim 26 , wherein the silicon carbide substrate is the first conductivity type and wherein forming the drain contact comprises forming the drain contact on the silicon carbide substrate.  
   
   
       28 . The method of  claim 24 , wherein the nitride-based semiconductor material comprises a GaN based semiconductor material.  
   
   
       29 . A method of fabricating a current aperture transistor comprising: 
 forming a first layer comprising semiconductor material of a second conductivity type or insulating on a substrate;    forming a channel layer comprising semiconductor material on the second layer;    forming a barrier layer on the channel layer;    forming a trench extending through the barrier layer, the channel layer and the first layer,    forming a region of semiconductor material of the first conductivity type in the trench;    forming a gate contact on the barrier layer;    forming a source contact on the barrier layer and opposite the trench from the gate contact; and    forming a drain contact electrically connected to the first layer.    
   
   
       30 . The method of  claim 29 , further comprising forming a second layer comprising semiconductor material of a first conductivity type on a substrate, wherein forming a first layer comprises forming a first layer on the second layer and wherein forming a trench comprises forming a trench extending through the barrier layer, the channel layer and the first layer and to the second layer.  
   
   
       31 . The method of  claim 29 , wherein the first conductivity type is n-type and the second conductivity type is p-type.  
   
   
       32 . The method of  claim 29 , wherein the semiconductor material comprises a nitride-based semiconductor material.  
   
   
       33 . The method of  claim 32 , wherein the substrate comprises gallium nitride.  
   
   
       34 . The method of  claim 32 , wherein the substrate comprises silicon carbide.  
   
   
       35 . The method of  claim 34 , wherein the silicon carbide substrate is the first conductivity type and wherein forming the drain contact comprises forming the drain contact on the silicon carbide substrate.  
   
   
       36 . The method of  claim 32 , wherein the nitride-based semiconductor material comprises a GaN based semiconductor material.  
   
   
       37 . The method of  claim 29 , further comprising forming an insulating layer between the gate contact and the barrier layer.  
   
   
       38 . The method of  claim 29 , further comprising forming contact regions of semiconductor material of the first conductivity type between the source contact and the barrier layer.  
   
   
       39 . The method of  claim 30 , wherein the trench extends into the second layer.  
   
   
       40 . The method of  claim 30 , further comprising forming a third layer comprising semiconductor material of the first conductivity type disposed between the substrate and the second layer comprising semiconductor material.